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Efficient SAT-Based Verification of Asynchronous System

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Informatics in Control, Automation and Robotics

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 133))

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Abstract

Bounded model checking has been recently introduced as an efficient verification method for reactive systems. This technique reduces model checking of linear temporal logic to propositional satisfiability. However this method does not work well for asynchronous systems. In this paper we propose a new SAT-based verification method for asynchronous systems. Our method can reduce verification time by representing the behavior by very succinct formulas.

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Author information

Authors and Affiliations

  1. Academic Research Department, Logistics Academy, Beijing, 100858, China

    Xu Yatao & Yuan Qin

  2. Logistics Command Department, Logistics Academy, Beijing, 100858, China

    Lin Changqing

  3. Computer Science Department, Jiangsu University, Zhenjiang, 212013, China

    Zhou Conghua

Authors
  1. Xu Yatao
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  2. Lin Changqing
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  3. Yuan Qin
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  4. Zhou Conghua
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Editor information

Editors and Affiliations

  1. Huazhong Normal Universiy, Hubei, People’s Republic China

    Dehuai Yang

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© 2011 Springer-Verlag Berlin Heidelberg

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Yatao, X., Changqing, L., Qin, Y., Conghua, Z. (2011). Efficient SAT-Based Verification of Asynchronous System. In: Yang, D. (eds) Informatics in Control, Automation and Robotics. Lecture Notes in Electrical Engineering, vol 133. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-25992-0_39

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  • DOI: https://doi.org/10.1007/978-3-642-25992-0_39

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-25991-3

  • Online ISBN: 978-3-642-25992-0

  • eBook Packages: EngineeringEngineering (R0)

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