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Assessing System Vulnerability Using Formal Verification Techniques

  • Görschwin Fey
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7119)

Abstract

Hardware systems are becoming more and more vulnerable to soft errors caused by radiation or process variations. Design techniques to cope with these problems are built into the system. But how to verify that the final system is as resilient as expected? The paper covers modeling issues related to assessing fault tolerance and reliability. Existing approaches are reviewed that analyze transient faults on the electrical as well as the logical level. Trade-offs regarding resource requirements and quality of results are discussed and the individual advantages are highlighted.

Keywords

Model Check Fault Tolerance Fault Model Boolean Network Soft Error 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Görschwin Fey
    • 1
  1. 1.Institute of Computer ScienceUniversity of BremenBremenGermany

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