A New Design of PC104 Host Controller Based on STM32F103

Abstract

In order to deal with some small scale or low power dissipation applications, this paper presents the STM32F103 as the core to construct PC104 host controller. This design can efficiently save costs, reduce power dissipation and enhance reliability. For hardware design, uses the rich General Purpose Input/output (GPIO) resources provided by STM32F103 to map address bus, data bus and control bus of PC104 bus. For software design, simulate PC104 bus by configure and operate the GPIO, and package the operation as library function for easy use. Use STM32F103 to simulate PC104 bus is proved to have high performance for its 72 MHz clock rate. The design has been tested on 8 bit and 16 bit PC104 bus functional card.