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Optimization of H.264/AVC Video Coding Based on DSP Platform

  • Yanfei Shen
  • JinTao Li
  • Zhenming Zhu
Chapter
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 128)

Abstract

Compared with the previous standards, the coding efficiency and coding performance of H.264/AVC are improved at the cost of higher computational complexity. This additional complexity complicates very much the implementation and optimization tasks of embedded real-time H.264/AVC video encoder. This paper introduces the method to develop and optimize the H.264/AVC encoder on the DSP hardware platform. The emphasis is put on the parallel and pipeline implementation of DCT, IDCT, ZigZag, Quantization, Inverse Quantization and context adaptive variable length coding (CAVLC) modules of H.264/AVC. Compared with previous work, it is characterized that the degree of code parallelism is improved through the reasonable arrange of data stream and module division without any loss in coding performance. The simulated results indicate that this efficient implementation can improve the speed of encoder by 30%.

Keywords

Video Code Register File Direct Memory Access Video Encoder Software Pipeline 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag GmbH Berlin Heidelberg 2012

Authors and Affiliations

  • Yanfei Shen
    • 1
    • 2
  • JinTao Li
    • 1
  • Zhenming Zhu
    • 1
  1. 1.Institute of Computing TechnologyChinese Academy of SciencesBeijingChina
  2. 2.Graduate University of Chinese Academy of SciencesBeijingChina

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