Optimization of H.264/AVC Video Coding Based on DSP Platform
Compared with the previous standards, the coding efficiency and coding performance of H.264/AVC are improved at the cost of higher computational complexity. This additional complexity complicates very much the implementation and optimization tasks of embedded real-time H.264/AVC video encoder. This paper introduces the method to develop and optimize the H.264/AVC encoder on the DSP hardware platform. The emphasis is put on the parallel and pipeline implementation of DCT, IDCT, ZigZag, Quantization, Inverse Quantization and context adaptive variable length coding (CAVLC) modules of H.264/AVC. Compared with previous work, it is characterized that the degree of code parallelism is improved through the reasonable arrange of data stream and module division without any loss in coding performance. The simulated results indicate that this efficient implementation can improve the speed of encoder by 30%.
KeywordsVideo Code Register File Direct Memory Access Video Encoder Software Pipeline
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