Design and Implementation of DVB-S2 LDPC Encoder

Chapter
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 127)

Abstract

In this paper, a DVB-S2 LDPC encoder based on FPGA is proposed after detailed analysis of DVB-S2 LDPC code on the basis of irregular repeat accumulate (IRA) coding algorithm. This method not only uses pipeline technique combined with all parallel structures to improve the coding efficiency, but also makes use of VHDL language to achieve DVB-S2 encoder, which meets the requirements of DVB-S2 standard on the condition of low hardware resources.

Keywords

DVB-S2 low density parity check code FPGA VHDL hardware description language 

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References

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Copyright information

© Springer-Verlag GmbH Berlin Heidelberg 2012

Authors and Affiliations

  1. 1.College of Physics and Information EngineeringFuzhou UniversityFuzhouChina

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