Design and Implementation of DVB-S2 LDPC Encoder
In this paper, a DVB-S2 LDPC encoder based on FPGA is proposed after detailed analysis of DVB-S2 LDPC code on the basis of irregular repeat accumulate (IRA) coding algorithm. This method not only uses pipeline technique combined with all parallel structures to improve the coding efficiency, but also makes use of VHDL language to achieve DVB-S2 encoder, which meets the requirements of DVB-S2 standard on the condition of low hardware resources.
KeywordsDVB-S2 low density parity check code FPGA VHDL hardware description language
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- 1.EN 302 307 V1.1.1 2004-06, Digital Video Broadcasting (DVB); Second Generation Framing Structure, Channel Coding and Modulation Systems for Broadcasting, Interactive Services, News Gathering and Other Broadband Satellite ApplicationsGoogle Scholar
- 2.Gallager, R.G.: Low density parity check code. IRE Trans. Inform. Theory IT-8, 21–28 (1962)Google Scholar
- 3.Xia, H.X., Ding, Y., Zhang, G.: Research of LDPC coding algorithm in DVB-S2. Modern Electronic Technology 13(228), 64–66 (2006)Google Scholar
- 4.Qi, M., Chen, Z.: Implementation of parallel LDPC coding in DVB-S2 system. Program Production and Broadcasting 31(11), 69–71 (2007)Google Scholar
- 5.Zhou, R., Tu, Y., Zhang, L.: Design examples of FPGA / CPLD digital system based on Quartus II, p. 34. Electronic Industry Press, Beijing (2007)Google Scholar