A Low-Swing Strategy in Multi-port Register File Design

  • Hao Yan
  • Yan Liu
  • Donghui Wang
  • Chaohuan Hou
Chapter
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 127)

Abstract

In this paper, a novel low-swing strategy is proposed for multi-port register file’s design. This low-swing strategy aims at single-ended bit line structure, and the low voltage swing is achieved by sensing and feedback in this strategy without additional inner chip voltage and reference voltage. This method contains two parts: writing and reading strategy. In WRITE low-swing scheme, the self-sense amplifier memory cell or modified memory cell can be used to support low-swing WRITE. The low-swing WRITE operation can save about 30.1% power. In READ low-swing scheme, a sense amplifier is also introduced. By using low-swing READ strategy, the power dissipated in READ is reduced to 48.1%, and the proposed sense amplifier also gives about 174ps sensing delay improvement.

Keywords

Threshold Voltage Memory Cell Register File Read Operation Schmitt Trigger 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    Zyuban, V., Kogge, P.: The energy complexity of register files. In: Proceedings of the 1998 International Symposium on Low Power Electronics and Design (ISLPED), pp. 305–310 (1998)Google Scholar
  2. [2]
    Mai, K.W., et al.: Low-power SRAM Design using Half-swing Pulse-mode Techniques. IEEE J. Solid-State Circuits 33, 1659–1671 (1998)CrossRefGoogle Scholar
  3. [3]
    Wang, J.-S., Tseng, W., Li, H.-Y.: Low-Power Embedded SRAM with the Current-Mode Write Technique. IEEE J. Solid-State Circuits 35, 119–124 (2000)CrossRefGoogle Scholar
  4. [4]
    Yang, B.-D., Kim, L.-S.: A low-power SRAM using Hierarchical Bit Line and Local Sense Amplifiers. IEEE Journal of Solid State Circuits 40, 1366–1376 (2005)CrossRefGoogle Scholar
  5. [5]
    Sharifkhani, M., Sachdev, M.: Segmented Virtual Ground Architecture for Low-Power Embedded SRAM. IEEE J. VLSI 15, 196–205 (2007)CrossRefGoogle Scholar
  6. [6]
    Tremblay, M., Joy, B., Shin, K.: A Three Dimensional Register File For Superscalar Processors. In: Proc. HICSS, pp. 191–201 (1995)Google Scholar
  7. [7]
    Yang, H.-I., et al.: A Low-Power Low-Swing Single-Ended Multi-Port SRAM. In: International Symposium on VLSI Design, Automation and Test, April 25-27 (2007)Google Scholar

Copyright information

© Springer-Verlag GmbH Berlin Heidelberg 2012

Authors and Affiliations

  • Hao Yan
    • 1
    • 2
  • Yan Liu
    • 1
  • Donghui Wang
    • 1
  • Chaohuan Hou
    • 1
  1. 1.Digital System Integration Lab, Institute of AcousticsChinese Academy of SciencesBeijingChina
  2. 2.Graduate University of Chinese Academy of SciencesBeijingChina

Personalised recommendations