Design and Realization of CDR and SerDes Circuit Used in BLVDS Controlling System
CDR(Clock and Data Recovery) and SerDes (Serializer/Deserializer) circuit is a critical circuit in the receiver of serial-data transceiver systems, and its performance affects the entire system’s function directly. This paper presents an improved scheme of the traditional dual-loop clock and data recovery circuit, which is based on special oversampling and in this scheme, the CDR and SerDes can be accomplished simultaneously. The proposed circuit is applied in a prototype system of BLVDS controlling, which consists of 5 nodes, with the longest distance of 131 meters, and speed of up to 20MHz, and through 380 tests, the circuit can work reliably, with lock time less than 10− 6s, and error rate lower than 10− 9.
KeywordsBLVDS clock & data recovery SerDes special over-sampling prototype system
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