Reed-Solomon Decoder Architecture Using Bit-Parallel Systolic Multiplier

  • Suvarna K. Gosavi
  • U. S. Ghodeswar
  • G. G. Sarate
Part of the Communications in Computer and Information Science book series (CCIS, volume 250)


Reed-Solomon (RS) codes play an important role in providing error protection and data integrity. Design of a scalable RS decoder is implemented with Bit-Parallel Systolic Multiplier. This bit-parallel multiplier is defined from All-One Polynomial. This can perform higher data throughput rate with shorter latency. As compared to other decoder architecture design the proposed work consist of less arithmetic operations and gate count is also comparably less.


RS Decoder Bit-Parallel All-One Polynomial 


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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Suvarna K. Gosavi
    • 1
  • U. S. Ghodeswar
    • 1
  • G. G. Sarate
    • 2
  1. 1.Yeshwantrao Chavan College of EngineeringNagpurIndia
  2. 2.Badnera College of EngineeringAmravatiIndia

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