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Ultra Low Power 50 nm SRAM for Temperature Invariant Data Retention

  • H. P. Rajani
  • Shrimannarayan Kulkarni
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 250)

Abstract

Power efficient SRAM cell with temperature invariant data retention is very vital component in the design of deep-submicron Static memories. A novel ultra low power stable 8T-SRAM cell for 50 nm CMOS technology is analyzed for data retention property in this paper. It exhibits power reduction both in active mode and standby modes of operation and ideal data retention at operating temperature range of -500C to 1500C. Two additional NMOS transistors, one each in the pull down path the two inverters of standard 6-T SRAM cell utilize self correcting feedback to provide this performance. During the active mode one of the inverters (OFF) utilizes stack effect and the other inverter (ON) uses cascode amplification property to reduce power dissipation. Sub threshold leakage power is reduced by utilizing stack effect in the idle mode. Simulations using BSIM 4 models for 50nm technology and supply voltage value of 0.5V, indicate about 23X power savings in active mode and 28 X times in stand-by(data-retention) mode at 500C. The logic 1 data of the SRAM cell is retained at 499.74 mV for VDD of 500mV during standby (data retention) mode.

Keywords

subthreshold leakage power stack effect active mode power data retention cascode amplification static random-access memory (SRAM) 

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References

  1. 1.
    Cho, M., Schlessman, J., Wolf, W., Mukhopadhyay, S.: Reconfigurable SRAM Architecture with Spatial Voltage Scaling for Low Power Mobile Multimedia Applications. IEEE Transactions on VLSI 19(1) (January 2011) Google Scholar
  2. 2.
    Goering, R.: Automating low power design– a progress report (September 2008), www.SCD.source.com
  3. 3.
    Roy, Mukhopadhyay, S., Mahmoodi, H., Meimand: Leakage Current Mechanisms and Leakage Reduction Techniques in Deep Sub micrometer CMOS Circuits. Proceedings of the IEEE 91(2) (February 2003) Google Scholar
  4. 4.
    Burd, T.D., Brodersen, R.W.: Design issues for dynamic voltage scaling. In: Proceedings of the 1998 International Symposium on Low Power Electronics and Design, pp. 9–14 (2000) Google Scholar
  5. 5.
    Park, J.C.: Sleepy Stack: a New Approach to Low Power VLSI Logic and Memory. A Thesis submitted at Georgia Institute of Technology (August 2005) Google Scholar
  6. 6.
    Powell, M.D., Yang, S.H., Falsafi, B., Roy, K., Vijaykumar, T.N.: Gated- VDD: A circuit technique to reduce leakage in cache memories. In: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (July 2000) Google Scholar
  7. 7.
    Agarwal, A., Li, H., Roy, K.: DRG-Cache: A data retention gated-ground cache for low power. In: Proceedings of the 39th Design Automation Conference (June 2002) Google Scholar
  8. 8.
    Nii, K., et al.: A 90-nm low-power 32 KB embedded SRAM with Gate Leakage Suppression Circuit for Mobile Applications. IEEE J. Solid-State Circuits 39(4), 684–693 (2004) Google Scholar
  9. 9.
    Flautner, K., et al.: Drowsy caches: simple techniques for reducing leakage power. In: International Symposium on Computer Architecture, pp. 148–157 (May 2002) Google Scholar
  10. 10.
    Nair, P., Eratne, S., John, E.: A Quasi Power Gated Low Leakage Stable SRAM Cell. In: 53rd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2010 (2010) Google Scholar
  11. 11.
    Rajani, H.P., Kulkarni, S.Y.: Novel Stable 8T SRAM for Power Minimization in Deep Submicron Cache Memories. In: Proceedings of International Conference on Emerging Trends in Engineering ICETE-II (May 2011) Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • H. P. Rajani
    • 1
  • Shrimannarayan Kulkarni
    • 2
  1. 1.K.L.E. Society’s College of Engineering & TechnologyBelgaumIndia
  2. 2.NMAM Institute of TechnologyNitteIndia

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