Abstract
This paper not only describes novel fast synchronization algorithms for HART C8PSK carrier recovery and symbol timing, but also provides a solution for HART C8PSK low power design. Synchronization is divided into two parts: initialization and tracking, the former part of which uses novel algorithms to attain equilibrium state quickly, and the later part of which is time-divided carried out. On basis of the proposed algorithms, high power component—equalizer and interpolator, can work at lowest rate, which indirectly reduces the system power. The implementation of those algorithms needs no additional hardware resource except a few lookup tables, and at the same time, they add negligible power consumption to the whole system. Simulations showed that the proposed synchronization algorithms can work very well in low SNR.
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References
Pratt, W.: The HART PSK Physical Layer. A Status Report to HCF Members, 6–7 (2000)
Schindler, V., Voltopia: HCF Working Group Meeting Minutes Salzburg. In: HART® Communication Foundation Document Number, Austria, February 9-11, pp. 52–59 (2009)
Kim, B., Greco, J.D., Helman, D.N., Ngo, H.: A high speed data separator design using real time DSP for disk drive applications. In: IEEE ISCAS, San Diego, CA, pp. 625–628 (May 1992)
Kim, B.: Digital carrier recovery with adaptive dual loop DPLL for mobile communication applications. In: IEEE ICASSP, Minneapolis, MN, vol. 3, pp. 29–32 (April 1993)
Rosemount, F.: High Speed HART Prototype Modem Project. In: Prepared for The HART Communication Foundation, USA, pp. 35–60 (1999)
Kim, B.: Dual-Loop DPLL Gear-Shifting Algorithm for Fast Synchronization. IEEE Transactions on Circuits and Systems—II: Analog and Digital Signal Processing 44(7), 577–586 (1997)
Huang, L., Luo, M., Dong, X.: A Fast Carrier Synchronization Algorithm for Burst-Mode MPSK. In: Third International Conference on Natural Computation, ICNC, pp. 167–170 (2007)
Andronico, M., Casale, S., La Corte, A., Pinnisi, C.: A New Algorithm for Fast Synchronization in a Burst Mode PSK Demodulator. In: 1995 IEEE International Conference on Communications, ICC 1995, Seattle, vol. 3, pp. 1641–1646 (1995)
Goto, H., Hasegawa, Y., Tanaka, M.: Efficient Scheduling Focusing on the Duality of MPL Representatives. In: Proc. IEEE Symp. Computational Intelligence in Scheduling (SCIS 2007), pp. 57–64. IEEE Press (December 2007), doi:10.1109/SCIS.2007.357670
Feng, W.-J., Hou, J.-H.: A new algorithm for symbol timing and carrier phase offset acquisition in burst communication. Journal of Circuits and Systems 13, 119–122 (2008)
Meyr, H., Moeneclaey, M., Fechtel, S.A.: Digital communication receiver, pp. 271–315. John Wiley & Sons, Inc., NewYork (1998)
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Zhenghua, J., Hong, W., Zhijia, Y. (2011). Low Complexity Synchronization Algorithms for HART C8PSK. In: Jiang, L. (eds) Proceedings of the 2011 International Conference on Informatics, Cybernetics, and Computer Engineering (ICCE2011) November 19-20, 2011, Melbourne, Australia. Advances in Intelligent and Soft Computing, vol 110. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-25185-6_84
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DOI: https://doi.org/10.1007/978-3-642-25185-6_84
Publisher Name: Springer, Berlin, Heidelberg
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