3D Stress Simulations of Nano Transistors

  • Abderrazzak El Boukili
Conference paper
Part of the Mathematics in Industry book series (MATHINDUSTRY, volume 17)


Mechanical Stress is intentionally used by many semiconductor device manufacturers as Intel, IBM, and TSMC to dramatically increase the performance of the new nano NMOS and PMOS transistors. Deposition induced stress is used to increase carrier mobility through the channel. This paper presents the three dimensional simulations and mathematical modeling of stress distribution after deposition of SiGe pockets in nano PMOS transistors. The originality of this work is to use Finite Volume discretization to solve stress equations in three dimensions and to use Multifrontal Method to solve the resulting large linear systems. Numerical results showing the 3D effects will be presented and analyzed for an Intel 45nm strained PMOS transistor.


Stress Equation PMOS Transistor SiGe Layer Shear Stress Component Silicon Germanium 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  1. 1.Al Akhawayn UniversityIfraneMorocco

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