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Compiler Support for Concurrency Synchronization

  • Tzong-Yen Lin
  • Cheng-Yu Lee
  • Chia-Jung Chen
  • Rong-Guey Chang
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7016)

Abstract

How to write a parallel program is a critical issue for Chip multi-processors (CMPs). To overcome the communication and synchronization obstacles of CMPs, transactional memory (TM) has been proposed as an alternative for controlling concurrency mechanism. Unfortunately, TM has led to seven performance pathologies: DuelingUpgrades, FutileStall, StarvingWriter, StarvingElder, SerializedCommit, RestartConvoy, and FriendlyFire. Such pathologies degrade performance during the interaction between workload and system. Although this performance issue can be solved by hardware, the software solution remains elusive. This paper proposes a priority scheduling algorithm to remedy these performance pathologies. By contrast, the proposed approach can not only solve this issue, but also achieve higher performance than hardware transactional memory (HTM) systems on some benchmarks.

Keywords

Transactional Memory Priority Schedule Dynamic Priority Hardware Solution Annual International Symposium 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Magnusson, P.S., et al.: Simics: A full system simulation platform. IEEE Computer, 50–58 (February 2002)Google Scholar
  2. 2.
    Ananian, C.S., Asanovic, K., Kuszmaul, B.C., Leiserson, C.E., Lie, S.: Unbounded transactional memory. In: Proceedings of the 11th International Symposium on High-Performance Computer Architecture, pp. 316–327 (January 2005)Google Scholar
  3. 3.
    Blasgen, M., Gray, J., Mitoma, M., Price, T.: The convoy phenomenon. SIGOPS Oper. Syst. Rev. 20–25 (1979)Google Scholar
  4. 4.
    Bobba, J., Moore, K.E., Volos, H., Yen, L., Hill, M.D., Swiftand, M.M., Wood, D.A.: Performance pathologies in hardware transactional memory. In: Proceedings of the 34th Annual International Symposium on Computer Architecture, pp. 387–394 (June 2007)Google Scholar
  5. 5.
    Carlstrom, B.D., McDonald, A., Chafi, H., Chung, J., Minh, C.C., Kozyrakis, C., Olukotun, K.: The atomoσ transactional programming language. In: Proceedings of the 2006 ACM SIGPLAN Conference on Programming Language Design and Implementation (June 2006)Google Scholar
  6. 6.
    Ceze, L., Tuck, J., Cascaval, C., Torrellas, J.: Bulk disambiguation of speculative threads in multiprocessors. In: Proceedings of the 33rd Annual International Symposium on Computer Architecture (June 2006)Google Scholar
  7. 7.
    Courtois, P.J., Heymans, F., Parnas, D.L.: Concurrent control with readers and writers. Communications of the ACM, 667–668 (1971)Google Scholar
  8. 8.
    Damron, P., Fedorova, A., Lev, Y., Luchango, V., Moir, M., Nussbaum, D.: Hybrid transactional memory. In: Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems (October 2006)Google Scholar
  9. 9.
    Gottschlich, J., Connors, D.A.: Extending contention managers for user-defined priority-based transactions. In: Proceedings of the 2008 Workshop on Exploiting Parallelism with Transactional Memory and other Hardware Assisted Methods (April 2008)Google Scholar
  10. 10.
    Hammond, L., Wong, V., Chen, M., Carlstrom, B.D., Davis, J.D., Hertzberg, B., Prabhu, M.K., Wijaya, H., Kozyrakis, C., Olukotun, K.: Transactional memory coherence and consistencys. In: Proceedings of the 31st Annual International Symposium on Computer Architecture (June 2004)Google Scholar
  11. 11.
    Herlihy, M., Moss, J.E.B.: Transactional memory: Architectural support for lock-free data structures. In: Proceedings of the 20th Annual International Symposium on Computer Architecture, pp. 289–300 (May 1993)Google Scholar
  12. 12.
    Scherer III, W.N., Scott, M.L.: Advanced contention management for dynamic software transactional memory. In: 24th ACM Symposium on Principles of Distributed Computing (July 2005)Google Scholar
  13. 13.
    Scherer III, W.N., Scott, M.L.: Randomization in stm contention management. In: Proceedings of the 24th ACM Symposium on Principles of Distributed Computing (July 2005)Google Scholar
  14. 14.
    Martin, M.M., Sorin, D.J., Beckmann, B.M., Marty, M.R., Min Xu, A.R.A., Moore, K.E., Hill, M.D., Wood, D.A.: Multifacet’s general execution-driven multiprocessor simulator toolset. In: Computer Architecture News, pp. 92–99 (September 2005)Google Scholar
  15. 15.
    Moore, K.E., Bobba, J., Moravan, M.J., Hill, M.D., Wood, D.A.: Log-based transactional memory. In: Proceedings of the 12th IEEE Symposium on High-Performance Computer Architecture, pp. 258–269 (February 2006)Google Scholar
  16. 16.
    Rajwar, R., Goodman, J.R.: Transactional lock-free execution of lock-based programs. In: Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (October 2002)Google Scholar
  17. 17.
    Woo, S.C., Ohara, M., Torrie, E., Singh, J.P., Gupta, A.: The splash-2 programs: Characterization and methodological considerations. In: Proceedings of the 22nd Annual International Symposium on Computer Architecture, pp. 24–37 (June 1995)Google Scholar
  18. 18.
    Yen, L., Bobba, J., Marty, M.R., Moore, K.E., Volos, H., Hill, M.D., Swift, M.M., Wood, D.A.: Logtm-se: Decoupling hardware transactional memory from caches. In: Proceedings of the 13th IEEE Symposium on High-Performance Computer Architecture, pp. 261–272 (February 2007)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Tzong-Yen Lin
    • 1
  • Cheng-Yu Lee
    • 1
  • Chia-Jung Chen
    • 1
  • Rong-Guey Chang
    • 1
  1. 1.Department of Computer ScienceNational Chung Cheng UniversityTaiwan

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