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Transactions on High-Performance Embedded Architectures and Compilers IV pp 1–20Cite as

A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors

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Part of the Lecture Notes in Computer Science book series (THIPEAC,volume 6760)

Abstract

Chip Multiprocessors (CMPs) mainly base their performance gains on exploiting thread-level parallelism. Consequently, powerful memory systems are needed to support an increasing number of concurrent threads. Conventional CMP memory systems do not account for thread interference which can result in reduced overall system performance. Therefore, conventional high bandwidth Miss Handling Architectures (MHAs) are not well suited to CMPs because they can create severe memory bus congestion. However, high miss bandwidth is desirable when sufficient bus bandwidth is available. This paper presents a novel, CMP-specific technique called the Adaptive Miss Handling Architecture (AMHA). If the memory bus is congested, AMHA improves performance by dynamically reducing the maximum allowed number of concurrent L1 cache misses of a processor core if this creates a significant speedup for the other processors. Compared to a 16-wide conventional MHA, AMHA improves performance by 12% on average for one of the workload collections used in this work.

Keywords

  • Clock Cycle
  • Processor Core
  • Performance Impact
  • Memory Latency
  • Acceptance Threshold

These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

This work was supported by the Norwegian Metacenter for Computational Science (NOTUR).

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Authors and Affiliations

  1. HiPEAC European Network of Excellence, Norwegian University of Science and Technology, Norway

    Magnus Jahre & Lasse Natvig

Authors
  1. Magnus Jahre
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  2. Lasse Natvig
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Editors and Affiliations

  1. Department of Computer Science and Engineering, Chalmers University of Technology, 412 96, Gothenburg, Sweden

    Per Stenström

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Jahre, M., Natvig, L. (2011). A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors. In: Stenström, P. (eds) Transactions on High-Performance Embedded Architectures and Compilers IV. Lecture Notes in Computer Science, vol 6760. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-24568-8_1

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  • DOI: https://doi.org/10.1007/978-3-642-24568-8_1

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