Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation

  • W. G. Osborne
  • W. Luk
  • J. G. F. Coutinho
  • O. Mencer
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6760)

Abstract

This paper describes a method of developing energy-efficient run-time reconfigurable hardware designs. The key idea is to systematically deactivate part of the hardware using word-length optimisation techniques, and then select the most optimal reconfiguration strategy: multiple bitstream reconfiguration or component multiplexing. When multiplexing between different parts of the circuit, it may not always be possible to gate the clock to the unwanted components in FPGAs. Different methods of achieving the same effect while minimising the area used for the control logic are investigated. A model is used to determine the conditions under which reconfiguring the bitstream is more energy-efficient than multiplexing part of the design, based on power measurements taken on 130nm and 90nm devices. Various case studies, such as ray tracing, B–Splines, vector multiplication and inner product are used to illustrate this approach.

Keywords

Power Consumption Power Loss Clock Frequency Energy Reduction Reduce Power Consumption 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • W. G. Osborne
    • 1
  • W. Luk
    • 1
  • J. G. F. Coutinho
    • 1
  • O. Mencer
    • 1
  1. 1.Department of ComputingImperial College LondonUK

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