A Modular Simulator Framework for Network-on-Chip Based Manycore Chips Using UNISIM

  • Xiongfei Liao
  • Wu Jigang
  • Thambipillai Srikanthan
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6760)


NoC-based manycore chips are considered as emerging platforms of significant importance but so far there is no public accessible architectural simulator which allows coupled simulation of NoC and cores for relevant research. This paper presents a modular cycle-level simulator framework developed using UNISIM and its applicability is exemplified by building a simulator which models a message-passing distributed memory architecture with an NoC and supports coupled simulation. Simulation of a MPI-based parallel program on this simulator shows that performance metrics, such as throughput, delay and overhead, can be accurately evaluated with the captured data of flits and messages. Simulators for different functionalities and architectures can be constructed by using this framework.


Network Interface Virtual Channel Couple Simulation Root Process Memory Request 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Xiongfei Liao
    • 1
  • Wu Jigang
    • 1
  • Thambipillai Srikanthan
    • 1
  1. 1.Centre for High Performance Embedded Systems, School of Computer EngineeringNanyang Technological UniversitySingapore

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