Synthesizing, Verifying, and Debugging SoC with FSM-Based Specification of On-Chip Communication Protocols
In general on-chip communication protocols, such as OCP, can be specified and represented with finite state machines (FSM). Such communication protocols are basically collections of individual transactions or commands, such as simple read/write and bust read/write, and each transaction or command can be specified with a FSM. So a given communication protocol can be represented with a set of FSMs which work jointly. Based on these FSM-based specifications, we have been developing not only pure formal and semi-formal verification techniques using FSMs as specifications, but also synthesis and debugging techniques, such as automatic generation of protocol converters and post-silicon verification/debugging supports. In this paper, we show first how FSM-based specifications can describe sate-of-the-art on-chip communication protocols, and then their application to such synthesis and verification/debug for SoC designs are presented.
KeywordsModel Check Clock Cycle Communication Protocol Finite State Machine Sequential Circuit
Unable to display preview. Download preview PDF.
- 1.Open Core Protocol International Partnership: Open Core Protocol Specification version 2.1Google Scholar
- 2.ARM: AMBA 3 AXI Specification v1.0Google Scholar
- 3.Passerone, R., Rowson, J.A., Vincentelli, A.S.: Automatic Synthesis of Interfaces between Incompatible Protocols. In: Proceedings of Design Automation Conference, pp. 8–13 (1998)Google Scholar
- 4.Watanabe, S., Seto, K., Ishikawa, Y., Komatsu, S., Fujita, M.: Protocol Transducer Synthesis using Divide and Conquer Approach. In: Proceedings of 12th Asia and South Pacific Design Automation Conference, pp. 280–285 (2007)Google Scholar
- 5.Lee, Y., Nishihara, T., Matsumoto, T., Fujita, M.: A Post-Silicon Debug Support Using High-level Design Description. In: Proc. of The 18th Asian Test Symposium, pp. 141–147 (November 2009)Google Scholar
- 6.Lee, Y., Matsumoto, T., Fujita, M.: Generation of I/O sequences for a high-level design from those in post-silicon for efficient post-silicon debugging. In: Proc. of International Conference on Computer Design, pp. 402–408 (October 2010)Google Scholar
- 7.Gharehbaghi, A.M., Fujita, M.: Transaction-Based Debugging of System-on-Chips with Patterns. In: Proc. of 27th IEEE International Conference on Computer Design, pp. 186–192 (October 2009)Google Scholar
- 8.Gharehbaghi, A.M., Fujita, M.: Global transaction ordering in Network-on-Chips for post-silicon validation. In: Proc. of International Symposium on Quality Electronic Design, pp. 284–289 (March 2011)Google Scholar