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Performance Impact of Task Mapping on the Cell BE Multicore Processor

  • Jörg Keller
  • Ana Lucia Varbanescu
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6161)

Abstract

Current multicores present themselves as symmetric to programmers with a bus as communication medium, but are known to be non-symmetric because their interconnect is more complex than a bus. We report on our experiments to map a simple application with communication in a ring to SPEs of a Cell BE processor such that performance is optimized. We find that low-level tricks for static mapping do not necessarily achieve optimal performance. Furthermore, we ran exhaustive mapping experiments, and we observed that (1) performance variations can be significant between consecutive runs, and (2) performance forecasts based on intuitive interconnect behavior models are far from accurate even for a simple communication pattern.

Keywords

Task Mapping Average Runtime Multicore Processor Cell Processor Unidirectional Ring 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Jörg Keller
    • 1
  • Ana Lucia Varbanescu
    • 2
  1. 1.University of HagenHagenGermany
  2. 2.Delft University of TechnologyDelftThe Netherlands

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