High Level Synthesis of Asynchronous Circuits from Data Flow Graphs

  • Rene van Leuken
  • Tom van Leeuwen
  • Huib Lincklaen Arriens
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6951)


This paper presents a toolbox for the automatic generation of asynchronous circuits starting from a data flow graph description. The toolbox consists of a scheduling and code generation tool. We use traditional scheduling algorithms as for synchronous circuits, but have replaced the implied synchronous controller for an asynchronous distributed control network. The control circuit allows for true asynchronous operation of all digital resources and as a result of its scalable distributed topology allows unlimited resource sharing. The distributed controllers can be created by connecting a small number of pre-designed sub-controllers which are presented in this paper. Prototype IP-blocks of these sub-controller circuits have been designed in a 90nm ASIC design process. Our toolbox is a capable to generate large complex asynchronous solutions, with upto 20 percent power saving, and as least as good latency performance as of synchronous solutions.


Finite Impulse Response Delay Element High Level Synthesis Data Flow Graph Schedule Result 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Rene van Leuken
    • 1
  • Tom van Leeuwen
    • 1
  • Huib Lincklaen Arriens
    • 1
  1. 1.Circuits and Systems Group, Faculty of Electrical Engineering, Mathematics and Computer ScienceDelft University of TechnologyDelftThe Netherlands

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