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A Framework for Architecture-Level Exploration of 3-D FPGA Platforms

  • Harry Sidiropoulos
  • Kostas Siozios
  • Dimitrios Soudris
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6951)

Abstract

Interconnection structures in FPGAs increasingly contribute more to the delay and power consumption. Three-dimensional (3-D) chip stacking is touted as the silver bullet technology that can keep Moore’s momentum and fuel the next wave of consumer electronics products. However, the benefits of such a technology have not been sufficiently explored yet. This paper introduces a novel 3-D FPGA, where logic, memory and I/O resources are assigned to different layers. Experimental results prove the efficiency of our architecture for a wide range of application domains, since we achieve average performance improvement and power saving of 30% and 10%, respectively.

Keywords

Memory Block Benchmark Suite Logic Resource Through Silicon Vias Heterogeneous Layer 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Harry Sidiropoulos
    • 1
  • Kostas Siozios
    • 1
  • Dimitrios Soudris
    • 1
  1. 1.School of Electrical and Computer EngineeringNational Technical University of AthensAthensGreece

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