Power and Area Optimization of 3D Networks-on-Chip Using Smart and Efficient Vertical Channels

  • Amir-Mohammad Rahmani
  • Kameswar Rao Vaddina
  • Pasi Liljeberg
  • Juha Plosila
  • Hannu Tenhunen
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6951)


3D NoC offers greater device integration, faster vertical interconnects and more power efficient inter-layer communication due to the beneficial attribute of short through silicon via (TSV) in 3D IC technologies. However, TSV pads used for bonding to a wafer layer, occupy significant chip area and result in routing congestions and expensive manufacturing process. This can lead to a significant reduction in 3D ICs’ yield and higher power densities compared to 2D NoCs. In this paper, a power-efficient and low-cost inter-layer communication scheme is proposed as one way to mitigate these challenges. Instead of using a pair of unidirectional channels for inter-layer communication, utilizing a high-performance bidirectional channel enables a system to benefit from low-latency nature of the vertical interconnects and to remarkably reduce the number of TSVs. Additionally, we present a forecasting-based dynamic frequency scaling technique for reducing the power consumption of the inter-layer communication. Our extensive simulations demonstrate significant area and power improvements compared to a typical symmetric 3D NoC.


Vertical Channel Link Utilization Average Power Consumption Dynamic Power Management Synopsys Design Compiler 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Amir-Mohammad Rahmani
    • 1
    • 2
  • Kameswar Rao Vaddina
    • 1
    • 2
  • Pasi Liljeberg
    • 1
  • Juha Plosila
    • 1
  • Hannu Tenhunen
    • 1
  1. 1.Computer Systems Lab., Department of Information TechnologyUniversity of TurkuFinland
  2. 2.Turku Centre for Computer Science (TUCS)Finland

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