Power and Area Optimization of 3D Networks-on-Chip Using Smart and Efficient Vertical Channels

  • Amir-Mohammad Rahmani
  • Kameswar Rao Vaddina
  • Pasi Liljeberg
  • Juha Plosila
  • Hannu Tenhunen
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6951)

Abstract

3D NoC offers greater device integration, faster vertical interconnects and more power efficient inter-layer communication due to the beneficial attribute of short through silicon via (TSV) in 3D IC technologies. However, TSV pads used for bonding to a wafer layer, occupy significant chip area and result in routing congestions and expensive manufacturing process. This can lead to a significant reduction in 3D ICs’ yield and higher power densities compared to 2D NoCs. In this paper, a power-efficient and low-cost inter-layer communication scheme is proposed as one way to mitigate these challenges. Instead of using a pair of unidirectional channels for inter-layer communication, utilizing a high-performance bidirectional channel enables a system to benefit from low-latency nature of the vertical interconnects and to remarkably reduce the number of TSVs. Additionally, we present a forecasting-based dynamic frequency scaling technique for reducing the power consumption of the inter-layer communication. Our extensive simulations demonstrate significant area and power improvements compared to a typical symmetric 3D NoC.

Keywords

Vertical Channel Link Utilization Average Power Consumption Dynamic Power Management Synopsys Design Compiler 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Jantsch, A., Tenhunen, H. (eds.): Networks on Chip. Kluwer Academic Publishers, Dordrecht (2003)Google Scholar
  2. 2.
    Feero, B.S., Pande, P.: Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation. IEEE Transactions on Computers 58(1), 32–45 (2009)MathSciNetCrossRefGoogle Scholar
  3. 3.
    Rahmani, A.-M., et al.: Congestion Aware, Fault Tolerant, and Thermally Efficient Inter-Layer Communication Scheme for Hybrid NoC-Bus 3D Architectures. In: Proc. of the NOCS 2011, pp. 65–72 (2011)Google Scholar
  4. 4.
    Muttersbach, J., et al.: Practical design of globally-asynchronous locally-synchronous systems. In: Proc. of the ASYNC 2000, pp. 52–59 (2000)Google Scholar
  5. 5.
    Ono, T., Greenstreet, M.: A modular synchronizing FIFO for NoCs. In: Proc. of the NOCS 2009, pp. 224–233 (2009)Google Scholar
  6. 6.
    Lu, Y.-C.: 3D technology based circuit and architecture design. In: Proc. of the ICCCAS 2009, pp. 1124–1128 (2009)Google Scholar
  7. 7.
    Loi, I., et al.: Developing Mesochronous Synchronizers to Enable 3D NoCs. In: Proc. of the DATE 2008, pp. 1414–1419 (2008)Google Scholar
  8. 8.
    Pasricha, S.: Exploring serial vertical interconnects for 3D ICs. In: Proc. of the DAC 2009, pp. 581–586 (2009)Google Scholar
  9. 9.
    Lan, Y.-C., et al.: BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel. In: Proc. of the NOCS 2009, pp. 266–275 (2009)Google Scholar
  10. 10.
    Cong, J., Zhang, Y.: Thermal via planning for 3-D ICs. In: Proc. of the ICCAD 2005, pp. 745–752 (2005)Google Scholar
  11. 11.
    Shang, L., et al.: Dynamic voltage scaling with links for power optimization of interconnection networks. In: Proc. of the HPCA 2003, pp. 91–102 (2003)Google Scholar
  12. 12.
    Tersine, R.J.: Principles of Inventory and Material Management. Prentice Hall PTR, Englewood Cliffs (1994)Google Scholar
  13. 13.
    Rahmani, A.-M., et al.: Forecasting-Based Dynamic Virtual Channel Management for Power Reduction in Network-on-Chips. Journal of Low Power Electronics 5(3), 385–395 (2009)CrossRefGoogle Scholar
  14. 14.
    Rahmani, A.-M., et al.: Power and performance optimization of voltage/frequency island-based networks-on-chip using reconfigurable synchronous/bi-synchronous FIFOs. In: Proc. of the CF 2010, pp. 267–276 (2010)Google Scholar
  15. 15.
    Bowker, A.H., Lieberman, G.J.: Engineering Statistics. Prentice Hall PTR, Englewood Cliffs (1972)Google Scholar
  16. 16.
    Rahmani, A.-M., et al.: NED: A Novel Synthetic Traffic Pattern for Power/Performance Analysis of Network-on-Chips Using Negative Exponential Distribution. Journal of Low Power Electronics 5, 396–405 (2009)CrossRefGoogle Scholar
  17. 17.
    Guindani, G., et al.: NoC Power Estimation at the RTL Abstraction Level. In: Proc. of the ISVLSI 2008, pp. 475–478 (2008)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Amir-Mohammad Rahmani
    • 1
    • 2
  • Kameswar Rao Vaddina
    • 1
    • 2
  • Pasi Liljeberg
    • 1
  • Juha Plosila
    • 1
  • Hannu Tenhunen
    • 1
  1. 1.Computer Systems Lab., Department of Information TechnologyUniversity of TurkuFinland
  2. 2.Turku Centre for Computer Science (TUCS)Finland

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