C-elements for Hardened Self-timed Circuits

  • Florent Ouchet
  • Katell Morin-Allory
  • Laurent Fesquet
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6951)

Abstract

Self-timed circuits are slope sensitive: when the voltage of one input or internal node changes too slowly, the interconnected logical blocks might loose their local one-to-one synchronization. This phenomenon often leads to unwanted global dead-locks of the entire circuit. The deep-submicronic manufacturing process mismatches might create such situations where one logical block is significantly slower than the others. We applied two known solutions for ensuring the correct C-element behavior whatever the slopes are: the transistors are resized and the supply voltage is reduced in order to guarantee the overall chip correctness taking into account the process variations.

Keywords

Threshold Voltage Logical Block NMOS Transistor PMOS Transistor Asynchronous Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Florent Ouchet
    • 1
  • Katell Morin-Allory
    • 1
  • Laurent Fesquet
    • 1
  1. 1.TIMA LaboratoryGrenoble INP, UJF, CNRSFrance

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