Power Profiling-Guided Floorplanner for Thermal Optimization in 3D Multiprocessor Architectures

  • Ignacio Arnaldo
  • José L. Risco-Martín
  • José L. Ayala
  • J. Ignacio Hidalgo
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6951)


3D integration has become one of the most promising techniques for the integration future multi-core processors, since it improves performance and reduces power consumption by decreasing global wire length. However, 3D integration causes serious thermal problems since the closer proximity of heat generating dies makes existing thermal hotspots more severe. Thermal-aware floorplanners can play an important role to improve the thermal profile, but they have failed in considering the dynamic power profiles of the applications. This paper proposes a novel thermal-aware floorplanner guided by the power profiling of a set of benchmarks that are representative of the application scope. The results show how our approach outperforms the thermal metrics as compared with the worst-case scenario usually considered in ”traditional” thermal-aware floorplanners.


Shared Memory Power Dissipation Mixed Integer Linear Program Wire Length Multiobjective Genetic Algorithm 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    Electrothermal monte carlo modelling of submicron hfets (2004),
  2. 2.
  3. 3.
    Adya, S., et al.: Fixed-outline floorplanning: enabling hierarchical design. IEEE Transactions on VLSI Systems 11(6), 1120–1135 (2003)CrossRefGoogle Scholar
  4. 4.
  5. 5.
    Berntsson, J., Tang, M.: A slicing structure representation for the multi-layer floorplan layout problem. In: Raidl, G.R., Cagnoni, S., Branke, J., Corne, D.W., Drechsler, R., Jin, Y., Johnson, C.G., Machado, P., Marchiori, E., Rothlauf, F., Smith, G.D., Squillero, G. (eds.) EvoWorkshops 2004. LNCS, vol. 3005, pp. 188–197. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  6. 6.
    Borkar, S.: Design challenges of technology scaling. IEEE Micro 19(4) (1999)Google Scholar
  7. 7.
    Chen, G., et al.: Partition-driven standard cell thermal placement (2003)Google Scholar
  8. 8.
    Chu, C., et al.: A matrix synthesis approach to thermal placement. IEEE Transactions on CADICS 17(11), 1166–1174 (1998)CrossRefGoogle Scholar
  9. 9.
    Coello, C., et al.: Evolutionary Algorithms for Solving Multi-Objective Problems. Kluwer, Dordrecht (2002)CrossRefzbMATHGoogle Scholar
  10. 10.
    Cong, J., et al.: A thermal-driven floorplanning algorithm for 3D ICs (2004)Google Scholar
  11. 11.
    Cuesta, D., Risco, J.L., Ayala, J.L., Atienza, D.: 3D Thermal-Aware Floorplanner for Many-Core Single-Chip Systems. In: IEEE Latin-American Test Workshop (2011)Google Scholar
  12. 12.
    Deb, K., et al.: A Fast and Elitist Multiobjective Genetic Algorithm: NSGA-II. IEEE Transactions on Evolutionary Computation 6(2), 182–197 (2002)CrossRefGoogle Scholar
  13. 13.
    Ekpanyapong, M., et al: Thermal-aware 3D microarchitectural floorplanning. Tech. rep., Georgia Institute of Technology Center (2004)Google Scholar
  14. 14.
    Han, Y., et al.: Simulated annealing based temperature aware floorplanning (2007)Google Scholar
  15. 15.
    Healy, M., et al.: Multiobjective microarchitectural floorplanning for 2D and 3D ICs. IEEE Transactions on CADICS 26(1), 38–52 (2007)MathSciNetCrossRefGoogle Scholar
  16. 16.
  17. 17.
    Hung, W.L., et al.: Thermal-aware floorplanning using genetic algorithms. In: ISQED, pp. 634–639 (March 2005)Google Scholar
  18. 18.
    IBM, C.D.C.: Complex soc design (2009)Google Scholar
  19. 19.
  20. 20.
    Iqbal, S., et al.: ParMiBench - an open-source benchmark for embedded multiprocessor systems. CAL 9(2), 45–48 (2010)Google Scholar
  21. 21.
    Li, X., et al.: A novel thermal optimization flow using incremental floorplanning for 3D ICs. In: ASPDAC, pp. 347–352. IEEE Press, Los Alamitos (2009)Google Scholar
  22. 22.
    Li, Y., et al.: Temperature aware floorplanning via geometry programming. In: IEEE International Conference on CSE Workshops, pp. 295–298 (July 2008)Google Scholar
  23. 23.
    Liu, Y., et al.: Accurate temperature-dependent integrated circuit leakage power estimation is easy. In: DATE, pp. 1526–1531 (2007)Google Scholar
  24. 24.
  25. 25.
    Paci, G., et al.: Exploring temperature-aware design in low-power MPSoCs. International Journal of Embedded Systems 3(1), 43–51 (2007)CrossRefGoogle Scholar
  26. 26.
    Sankaranarayanan, K., et al.: A case for thermal-aware floorplanning at the microarchitectural level. JILP 7(1), 8–16 (2005)Google Scholar
  27. 27.
    Singhal, L., et al.: Statistical power profile correlation for realistic thermal estimation. In: ASP-DAC, pp. 67–70. IEEE Computer Society Press, Los Alamitos (2008)Google Scholar
  28. 28.
    Tang, M., et al.: A memetic algorithm for VLSI floorplanning. IEEE Transactions on Systems, Man, and Cybernetics, Part B 37(1), 62–69 (2007)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Ignacio Arnaldo
  • José L. Risco-Martín
  • José L. Ayala
  • J. Ignacio Hidalgo

There are no affiliations available

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