Using Silent Writes in Low-Power Traffic-Aware ECC

  • Mostafa Kishani
  • Amirali Baniasadi
  • Hossein Pedram
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6951)


Using Error Detection Code (EDC) and Error Correction Code (ECC) is a noteworthy way to increase cache memories robustness against soft errors. EDC enables detecting errors in cache memory while ECC is used to correct erroneous cache blocks.

ECCs are often costly as they impose considerable area and energy overhead on cache memory. Reducing this overhead has been the subject of many studies. In particular, a previous study has suggested mapping ECC to the main memory at the expense of high cache traffic and energy. A major source of this excessive traffic and energy is the high frequency of cache writes. In this work, we show that a significant portion of cache writes are silent, i.e., they write the same data already existing. We build on this observation and introduce Traffic-aware ECC (or simply TCC). TCC detects silent writes by an efficient mechanism. Once such writes are detected updating their ECC is avoided effectively reducing L2 cache traffic and access frequency.

Using our solution, we reduce L2 cache access frequency by 8% while maintaining performance. We reduce L2 cache dynamic and overall cache energy by up to 32% and 8%, respectively. Furthermore, TCC reduces L2 cache miss rate by 3%.


Data Block Conventional System Error Correction Code Data Cache Cache Line 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    Yoon, D.H., Erez, M.: Memory mapped ECC: low-cost error protection for last level caches. In: International Symposium on Computer Architecture (ISCA), pp. 116–127 (2009)Google Scholar
  2. 2.
    Zhang, W., Gurumurthi, S., Kandemir, M., Sivasubramaniam, A.: ICR: In-Cache Replication for Enhancing Data Cache Reliability. In: International Conference on Dependable Systems and Networks, DSN (June 2003)Google Scholar
  3. 3.
    Kim, S., Somani, A.K.: Area Efficient Architectures for Information Integrity in Cache Memories. In: International Symposium on Computer Architecture, ISCA (May 1999)Google Scholar
  4. 4.
    Sadler, N.N., Sorin, D.J.: Choosing an Error Protection Scheme for a Microprocessor’s L1 Data Cache. In: International Conference on Computer Design, ICCD (October 2006)Google Scholar
  5. 5.
    Li, L., Degalahal, V.S., Vijaykrishnan, N., Kaandemir, M., Irwin, M.J.: Soft Error and Energy Consumption Interactions: A Data Cache Perspective. In: International Symposium on Low Power Electronics and Design, ISLPED (August 2004)Google Scholar
  6. 6.
    Kim, S.: Area-Efficient Error Protection for Caches. In: Conference on Design Automation and Test in Europe, DATE (March 2006)Google Scholar
  7. 7.
    Lepak, K.M., Lipasti, M.H.: Silent stores for free. In: ACM/IEEE International Symposium on Microarchitecture, pp. 22–31 (December 2000)Google Scholar
  8. 8.
    Burger, D., Austin, T.M.: The SimpleScalar tool set, version 2.0. ACM SIGARCH Computer Architecture News 25(3), 13–25 (1997)CrossRefGoogle Scholar
  9. 9.
  10. 10.
    Muralimanohar, N., Balasubramonian, R., Jouppi, N.P.: Architecting Efficient Interconnects for Large Caches with CACTI 6.0. MICRO 28(1), 69–79 (2008)Google Scholar
  11. 11.
    Perelman, E., Hamerly, G., Biesbrouck, M.V., Sherwood, T., Calder, B.: Using SimPoint for Accurate and Efficient Simulation. In: ACM SIGMETRICS the International Conference on Measurement and Modeling of Computer Systems (June 2003)Google Scholar
  12. 12.
    Karlsson, J., Ledan, P., Dahlgren, P., Johansson, R.: Using heavy-ion radiation to validate fault handling mechanisms. MICRO, 8–23 (February 1994)Google Scholar
  13. 13.
    Sosnowski, J.: Transient fault tolerance in digital systems. MICRO, 24–35 (February 1994)Google Scholar
  14. 14.
    Scheick, L.Z., Guertin, S.M., Swift, G.M.: Analysis of Radiation Effects on Individual DRAM Cells. IEEE Transact. Nucl. Sci. 47(6), 2534–2545 (2000)CrossRefGoogle Scholar
  15. 15.
    Standards, J.: JESD89 Measurement and Reporting of Alpha Particles and Terrestrial Cosmic Ray-Induced Soft Errors in Semiconductor Devices, JESD89-1 System Soft Error Rate (SSER) Method and JESD89-2 Test Method for Alpha Source Accelerated Soft Error Rate (2001)Google Scholar
  16. 16.
    Gordon, M.S., Rodbell, K.P., Heidel, D.F., Cabral Jr., C., Cannon, E.H., Reinhardt, D.D.: Single-event-upset and alpha-particle emission rate measurement techniques. IBM Journal of Research and Development 52(3) (May 2008)Google Scholar
  17. 17.
    Maiz, J., Hareland, S., Zhang, K., Armstrong, P.: Characterization of Multi-Bit Soft Error Events in Advanced SRAMs. In: IEEE International Electron Devices Meeting, IEDM (December 2003)Google Scholar
  18. 18.
    Slayman, C.W.: Cache and memory error detection, correction, and reduction techniques for terrestrial servers and workstations. IEEE Trans. on Reliability 5(3), 397–404 (2005)Google Scholar
  19. 19.
  20. 20.
    Kalla, R., Balaram, S., Tendler, J.M.: IBM Power5 chip: a dual-core multithreaded processor. MICRO, 40–47 (March-April 2004)Google Scholar
  21. 21.
  22. 22.

Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Mostafa Kishani
    • 1
  • Amirali Baniasadi
    • 2
  • Hossein Pedram
    • 1
  1. 1.Department of Computer Engineering and Information TechnologyAmirkabir University of TechnologyIran
  2. 2.Electrical & Computer EngineeringUniversity of VictoriaCanada

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