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Software Logical Structure Verification Method by Modeling Implemented Specification

  • Conference paper
Knowledge-Based and Intelligent Information and Engineering Systems (KES 2011)

Part of the book series: Lecture Notes in Computer Science ((LNAI,volume 6883))

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Abstract

In component testing for a single function, a functional black box testing based on specification of the function and a white box testing based on the program structure are performed. However, It is difficult to verify a logical correctness of the program by these testing methods. In this paper, a novel verification method to achieve it is proposed. Conventional testing usually compares output from program with expected output, our method models the function specification and the implemented specification as a Decision Table format, then compare them. We applied this method to some commercial programs. As a result, we could verify correctness of the logics implemented in the programs.

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Author information

Authors and Affiliations

  1. Graduate School of Systems and Information Engineering, University of Tsukuba, Japan

    Keiji Uetsuki & Kazuhiko Tsuda

  2. Debug Engineering Institute, Japan

    Tohru Matsuodani

Authors
  1. Keiji Uetsuki
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  2. Tohru Matsuodani
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  3. Kazuhiko Tsuda
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Editor information

Editors and Affiliations

  1. Institute of Integrated Sensor Systems, University of Kaiserslautern, Erwin-Schroedinger-str. 12, 67663, Kaiserslautern, Germany

    Andreas König

  2. Knowledge-Based Systems Group, Department of Computer Science, University of Kaiserslautern, P.O. Box 3049, 67653, Kaiserslautern, Germany

    Andreas Dengel

  3. School of Business, University of Applied Sciences Northwestern Switzerland, Riggenbachstr. 16, 4600, Olten, Switzerland

    Knut Hinkelmann

  4. Graduate School of Engineering, Osaka Prefecture University, 1-1 Gakuen-cho, Sakai, 599-8531, Osaka, Japan

    Koichi Kise

  5. KES International, P.O. Box 2115, BN43 9AF, Shoreham-by-sea, UK

    Robert J. Howlett

  6. University of South Australia, Adelaide, 5095, Mawson Lakes, SA, Australia

    Lakhmi C. Jain

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© 2011 Springer-Verlag Berlin Heidelberg

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Uetsuki, K., Matsuodani, T., Tsuda, K. (2011). Software Logical Structure Verification Method by Modeling Implemented Specification. In: König, A., Dengel, A., Hinkelmann, K., Kise, K., Howlett, R.J., Jain, L.C. (eds) Knowledge-Based and Intelligent Information and Engineering Systems. KES 2011. Lecture Notes in Computer Science(), vol 6883. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-23854-3_36

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  • DOI: https://doi.org/10.1007/978-3-642-23854-3_36

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-23853-6

  • Online ISBN: 978-3-642-23854-3

  • eBook Packages: Computer ScienceComputer Science (R0)

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