A Dynamic Power-Aware Partitioner with Task Migration for Multicore Embedded Systems

  • José Luis March
  • Julio Sahuquillo
  • Salvador Petit
  • Houcine Hassan
  • José Duato
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6852)


Nowadays, a key design issue in embedded systems is how to reduce the power consumption, since batteries have a limited energy budget. For this purpose, several techniques such as Dynamic Voltage Scaling (DVS) or task migration can be used. DVS allows reducing power by selecting the optimal voltage supply, while task migration achieves this effect by balancing the workload among cores.

This paper first analyzes the impact on energy due to task migration in multicore embedded systems with DVS capability and using the well-known Worst Fit (WF) partitioning heuristic. To reduce overhead, migrations are only performed at the time that a task arrives to and/or leaves the system and, in such a case, only one migration is allowed.

The huge potential on energy saving due to task migration, leads us to propose a new dynamic partitioner, namely DP, that migrates tasks in a more efficient way than typical partitioners. Unlike WF, the proposed algorithm examines which is the optimal target core before allowing a migration. Experimental results show that DP can improve energy consumption in a factor up to 2.74 over the typical WF algorithm.


IEEE Computer Society Dynamic Voltage Scaling Workload Balance Task Migration Task Queue 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • José Luis March
    • 1
  • Julio Sahuquillo
    • 1
  • Salvador Petit
    • 1
  • Houcine Hassan
    • 1
  • José Duato
    • 1
  1. 1.Department of Computer Engineering (DISCA)Universitat Politècnica de ValènciaSpain

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