From Assertion-Based Verification to Assertion-Based Synthesis

  • Yann Oddos
  • Katell Morin-Allory
  • Dominique Borrione
Part of the IFIP Advances in Information and Communication Technology book series (IFIPAICT, volume 360)


We propose a linear complexity approach to achieve automatic synthesis of designs from temporal specifications. It uses concepts from the Assertion-Based Verification. Each property is turned into a component combining classical monitor and generator features: the extended-generator. We connect them with specific components to obtain a design that is correct by construction. It shortens the design flow by removing implementation and functional verification steps. Our approach synthesizes circuits specified by hundreds of temporal properties in a few seconds. Complex examples (i.e. conmax-ip and GenBuf) show the efficiency of the approach.


Assertion Based Verification Assertion Based Synthesis PSL LTL High-level Automatic Synthesis Monitors Generators 


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Copyright information

© IFIP International Federation for Information Processing 2011

Authors and Affiliations

  • Yann Oddos
    • 1
  • Katell Morin-Allory
    • 1
  • Dominique Borrione
    • 1
  1. 1.TIMA Laboratory (CNRS/Grenoble-INP/UJF)Grenoble CEDEXFrance

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