Advertisement

From Assertion-Based Verification to Assertion-Based Synthesis

  • Yann Oddos
  • Katell Morin-Allory
  • Dominique Borrione
Part of the IFIP Advances in Information and Communication Technology book series (IFIPAICT, volume 360)

Abstract

We propose a linear complexity approach to achieve automatic synthesis of designs from temporal specifications. It uses concepts from the Assertion-Based Verification. Each property is turned into a component combining classical monitor and generator features: the extended-generator. We connect them with specific components to obtain a design that is correct by construction. It shortens the design flow by removing implementation and functional verification steps. Our approach synthesizes circuits specified by hundreds of temporal properties in a few seconds. Complex examples (i.e. conmax-ip and GenBuf) show the efficiency of the approach.

Keywords

Assertion Based Verification Assertion Based Synthesis PSL LTL High-level Automatic Synthesis Monitors Generators 

References

  1. [ABBSV00]
    Aziz, A., Balarin, F., Brayton, R.-K., Sangiovanni-Vincentelli, A.-L.: Sequential synthesis using S1S. IEEE Trans. on CAD of Integrated Circuits and Systems 19(10), 1149–1162 (2000)CrossRefGoogle Scholar
  2. [ABC+]
    Anderson, T., Bergeron, J., Cerny, E., Hunter, A., Nightingale, A.: Systemverilog reference verification methodology: Introduction. EE Times, March 27 (2006)Google Scholar
  3. [BCE+04]
    Bloem, R., Cavada, R., Eisner, C., Pill, I., Roveri, M., Semprini, S.: Manual for property simulation and assurance tool (deliverable 1.2/4-5). Technical report, PROSYD Project (January 2004)Google Scholar
  4. [BCZ06]
    Boulé, M., Chenard, J.-S., Zilic, Z.: Adding debug enhancements to assertion checkers for hardware emulation and silicon debug. In: Proceedings of the 24th International Conference on Computer Design, ICCD 2006 (October 2006)Google Scholar
  5. [BGJ+07]
    Bloem, R., Galler, S., Jobstman, B., Piterman, N., Pnueli, A., Weiglhofer, M.: Specify, compile, run: Hardware from PSL. Electronic Notes in Theoretical Computer Science (ENTCS) 190 (2007)Google Scholar
  6. [Cal05]
    Calamé, J.R.: Specification-based test generation with TGV. Technical Report R0508, Centrum voor Wiskunde en Informatica (May 2005)Google Scholar
  7. [CRST06]
    Cimatti, A., Roveri, M., Semprini, S., Tonetta, S.: From PSL to NBA: a Modular Symbolic Encoding. In: Proceedings of IEEE Formal Methods for Computer Aided Design, FMCAD 2006, November 11-12, pp. 125–133 (2006)Google Scholar
  8. [CVK04]
    Cohen, B., Venkataramanan, S., Kumari, A.: Using PSL/Sugar for Formal and Dynamic Verification. VhdlCohen Publishing (2004)Google Scholar
  9. [DGV99]
    Daniele, M., Giunchiglia, F., Vardi, M.: Improved Automata Generation for Linear Temporal Logic. In: Halbwachs, N., Peled, D.A. (eds.) CAV 1999. LNCS, vol. 1633, pp. 249–260. Springer, Heidelberg (1999)CrossRefGoogle Scholar
  10. [FKL03]
    Foster, H., Krolnik, A., Lacey, D.: Assertion-Based Design. Kluwer Academic Publishers, Dordrecht (2003)Google Scholar
  11. [FU82]
    Floyd, R.-W., Ullman, J.D.: The compilation of regular expressions into integrated circuits. J. ACM 29(3), 603–622 (1982)MathSciNetMATHCrossRefGoogle Scholar
  12. [FWMG05]
    Foster, H., Wolfshal, Y., Marschner, E., IEEE 1850 Work Group: IEEE standard for property specification language PSL. pub-IEEE-STD, pub-IEEE-STD:adr (October 2005)Google Scholar
  13. [GO01]
    Gastin, P., Oddoux, D.: Fast LTL to Büchi automata translation. In: Berry, G., Comon, H., Finkel, A. (eds.) CAV 2001. LNCS, vol. 2102, p. 53. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  14. [Her02]
    Herveille, R.: WISHBONE system-on-chip (SoC) interconnection architecture for portable IP cores. Technical report (September 2002), http://www.opencores.org/projects.cgi/web/wishbone/wbspec_b3.pdf
  15. [HIL04]
    Haifa-IBM-Laboratories. RuleBase Parallel Edition. IBM (November 2004)Google Scholar
  16. [IBM]
    IBM. PSL/Sugar-based Verification Tools. Web page, http://www.haifa.il.ibm.com/projects/verification/sugar/tools.html
  17. [MAB06]
    Morin-Allory, K., Borrione, D.: Proven correct monitors from PSL specifications. In: DATE 2006 (January 2006)Google Scholar
  18. [MAB07]
    Morin-Allory, K., Borrione, D.: On-line monitoring of properties built on regular expressions sequences. In: Vachoux, A. (ed.) Applications of Specification and Design Languages for SoCs. Springer, Heidelberg (2007)Google Scholar
  19. [Öbe99]
    Öberg, J.: ProGram: A Grammar-Based Method for Specification and Hardware Synthesis of Communication Protocols. PhD thesis, Royal Institue of Technologoy - Department of Electronics, Eletronic System Design, Sweden (1999)Google Scholar
  20. [Odd09]
    Oddos, Y.: PSL Specification for the WISHBONE Interconnect Matrix IP Core (2009), http://tima.imag.fr/vds/horus/synthorus_specs/
  21. [OMAB06]
    Oddos, Y., Morin-Allory, K., Borrione, D.: On-line test vector generation from temporal constraints written in PSL. In: Proc. VLSI SoC 2006 (2006)Google Scholar
  22. [PRO]
    PROSYD. Tools and techniques for property verification. Web page, http://www.prosyd.org/twiki/view/Public/DeliverablePageWP3
  23. [SB94]
    Seawright, A., Brewer, F.: Clairvoyant: A synthesis system for production-based specification. IEEE Trans. on VLSI, 172–185 (June 1994)Google Scholar
  24. [SM02]
    Siegmund, R., Müller, D.: Automatic synthesis of communication controller hardware from protocol specifications. IEEE Design & Test of Computers 19(4), 84–95 (2002)CrossRefGoogle Scholar
  25. [SMB+05]
    Srouji, J., Mehta, S., Brophy, D., Pieper, K., Sutherland, S., IEEE 1800 Work Group: IEEE Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language. pub-IEEE-STD, pub-IEEE-STD:adr (November 2005)Google Scholar
  26. [SNBE07]
    Schickel, M., Nimbler, V., Braun, M., Eveking, H.: An Efficient Synthesis Method for Property-Based Design in Formal Verification: On Consistency and Completeness of Property-Sets. In: Advances in Design and Specification Languages for Embedded Systems, pp. 179–196. Springer, Netherlands (2007), 978-1-4020-6149-3 CrossRefGoogle Scholar
  27. [SOSE08]
    Schickel, M., Oberkönig, M., Schweikert, M., Eveking, H.: A case-study in property-based synthesis: Generating a cache controller from property-set. In: Villar, E. (ed.) Embedded Systems Specification and Design Languages, pp. 271–275. Springer, Netherlands (2008)CrossRefGoogle Scholar
  28. [ST03]
    Sebastiani, R., Tonetta, S.: More Deterministic vs Smaller Büchi Automata for Efficient LTL Model Checking. In: Geist, D., Tronci, E. (eds.) CHARME 2003. LNCS, vol. 2860, pp. 126–140. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  29. [Uss02]
    Usselman, R.: WISHBONE Interconnect Matrix IP Core (2002), http://www.opencores.org/projects.cgi/web/wb_conmax/overview
  30. [YJC04]
    Yen, C., Jou, J., Chen, K.: A divide-and-conquer-based algorithm for automatic simulation vector generation. IEEE Design & Test of Computers 21(2), 111–120 (2004)CrossRefGoogle Scholar

Copyright information

© IFIP International Federation for Information Processing 2011

Authors and Affiliations

  • Yann Oddos
    • 1
  • Katell Morin-Allory
    • 1
  • Dominique Borrione
    • 1
  1. 1.TIMA Laboratory (CNRS/Grenoble-INP/UJF)Grenoble CEDEXFrance

Personalised recommendations