Abstract
By 2020 it is very likely that nano-CMOS will reach the end of the scaling roadmap. Such end will not mean the demise of silicon technology at all. While there are uncertainties as to what will be the show-stoppers, there is a large number of transitional and compatible to CMOS technologies that will be more important than just 2-D scaling. This paper discusses possible limitations bringing the end of scaling and also proposes a likely scenario for hardware technology evolution and related challenges for integrating systems in the next 20 years. The scenario beyond the end of the roadmap is drawn, in which key technologies will be developed to be compatible with nano-scaled CMOS in silicon, and not to replace it entirely. Transitional technologies will rather co-exist and be built upon a basic CMOS-like technology platform of silicon-on-insulator. Radically new devices at the 1-10 nm scale will most likely be built on a silicon substrate with the same technical requirements (such as cleanness, lithographic resolution, long-range ordering, etc) of near end-of-roadmap CMOS industry. The end of scaling will not necessarily lead to the onset of a post-silicon era. Advanced materials research has not pointed so far to a non-silicon scenario well beyond 2020. The computing systems challenges will be dealt with new forms of integration, hierarchically ordered from the micron-level, to sub-micron level (500nm to 100nm) non-digital, down to nano-scaled transistors on silicon further down to 10 nm. In this hierarchy, at the bottom, it is highly possible that disruptive molecular-level devices (self-assembled in the scale of 2 to 10 nanometers) will eventually be production-worthy for 100 Giga- to Tera-scale devices integration. Structures like graphene-based carbon tubes or planes are the most viable candidates for molecular devices. In this presentation the computer-systems relevant issues of systems power dissipation, noise, hardware design complexity, and resilience to systems failures in the presence of device variances and faults, are addressed as the challenging computing research topics that will guide future research in computing architectures at the tera-scale integration beyond 2020.
Chapter PDF
Similar content being viewed by others
References
Kilby, J.: US Patent (1959)
Brazilian Computer Society: Grand Challenges in Computer Science Research in Brazil 2006-2016, Brazil, pgs 25 (2006), http://www.sistemas.sbc.org.br (last accessed December 22,2008)
International Roadmap Committee. The International Technology Roadmap for Semiconductors - 2009 (2009), www.itrs.net (last accessed January 18, 2010)
Gartner Group (2008), http://www.eweek.com/c/a/ Desktop...Chip-Revenue....Semiconductor-Industry (last accessed February 09, 2009)
Hiroshi, I.: Future of CMOS Technology and Manufacturing. EEE DL talk at Federal University of Rio Grande do Sul, mimeo, p. 105 (2007)
Reis, R.: Design Automation of Transistor Networks, a New Challenge. In: IEEE International Symposium on Circuits and Systems, ISCAS 2011, Rio de Janeiro, Brazil, May 15-19, pp. 2485–2488. IEEE Press, Los Alamitos (2011) ISBN: 978-1-4244-9472-9
Detjens, E., et al.: Technology Mapping in MIS. In: IEEE ICCAD, pp. 116–119 (1987)
Ziesemer, A., Lazzari, C., Reis, R.: Transistor Level Automatic Layout Generator for non-Complementary CMOS Cells. In: International Conference on Very Large Scale Integration, IFIP/CEDA VLSI-SoC 2007, pp. 116–121 (2007)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2011 IFIP International Federation for Information Processing
About this paper
Cite this paper
Bampi, S., Reis, R. (2011). Challenges and Emerging Technologies for System Integration beyond the End of the Roadmap of Nano-CMOS. In: Becker, J., Johann, M., Reis, R. (eds) VLSI-SoC: Technologies for Systems Integration. VLSI-SoC 2009. IFIP Advances in Information and Communication Technology, vol 360. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-23120-9_2
Download citation
DOI: https://doi.org/10.1007/978-3-642-23120-9_2
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-23119-3
Online ISBN: 978-3-642-23120-9
eBook Packages: Computer ScienceComputer Science (R0)