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From Sizing over Design Centering and Pareto Optimization to Tolerance Pareto Optimization of Electronic Circuits

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Scientific Computing in Electrical Engineering SCEE 2010

Part of the book series: Mathematics in Industry ((TECMI,volume 16))

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Abstract

This paper presents an overview of sizing tasks in electronic circuit design and their corresponding formulations as optimization problems. We will start with the general multi-objective sizing problem. Then, the inclusion of statistically distributed parameters and of range-valued parameters into the scalar problems of yield optimization and design centering will be described. Finally, a problem formulation for considering these parameter tolerances by multi-objective Pareto optimization will be presented.

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References

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Correspondence to Helmut Gräb .

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Gräb, H. (2012). From Sizing over Design Centering and Pareto Optimization to Tolerance Pareto Optimization of Electronic Circuits. In: Michielsen, B., Poirier, JR. (eds) Scientific Computing in Electrical Engineering SCEE 2010. Mathematics in Industry(), vol 16. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-22453-9_4

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