Skip to main content

HPC Systems at JAIST and Development of Dynamic Loop Monitoring Tools Toward Runtime Parallelization

  • Conference paper
  • First Online:
High Performance Computing on Vector Systems 2011
  • 695 Accesses

Abstract

This manuscript describes a brief introduction of information environment and HPC machines at JAIST (Japan Advanced Institute of Science and Technology) and shows our efforts to achieve effective parallel processing on these platform composed of a wide variety of heterogeneous HPC machines. As an example of our efforts, we present an infrastructure that monitors dynamic loop nests and detect data dependences. We demonstrate that these provide not only useful hints for compilers and expert parallel programmers but also the inevitable for runtime parallelization with speculative executions.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 109.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 149.00
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 139.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Aho, A.V., Lam, M.S., Sethi, R., Ullman, J.D.: Compilers: Principles, Techniques, and Tools (2nd Edition). Addison Wesley (2006)

    Google Scholar 

  2. Ammons, G., et al.: Exploiting hardware performance counters with flow and context sensitive profiling. In: Proceedings of the ACM SIGPLAN 1997 conference on Programming language design and implementation, pp. 85–96 (1997)

    Google Scholar 

  3. Chen, T., J.Lin, W.Hsu, Yew, P.C.: Data dependence profiling for speculative optimization. In: In The Proceedings of the 14th International Conference on Compiler Construction, pp. 57–62 (2004)

    Google Scholar 

  4. Cormen, T.H., Leiserson, C.E., Rivest, R.L., Stein, C.: Introduction to Algorithms, Third Edition. The MIT Press (2009)

    MATH  Google Scholar 

  5. Havlak, P.: Nesting of reducible and irreducible loops. ACM Trans. Program. Lang. Syst. 19(4), 557–567 (1997)

    Article  Google Scholar 

  6. Liao, C., et al.: Effective source-to-source outlining to support whole program empirical optimization. In: The 22nd International Workshop on Languages and Compilers for Parallel Computing (2009)

    Google Scholar 

  7. Lin, J., Chen, T., Hsu, W.C., Yew, P.C., Ju, R.D.C., Ngai, T.F., Chan, S.: A compiler framework for speculative optimizations. ACM Trans. Archit. Code Optim. 1(3), 247–271 (2004)

    Article  Google Scholar 

  8. Luk, C.K., et al.: Pin: building customized program analysis tools with dynamic instrumentation. In: Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation, pp. 190–200 (2005)

    Google Scholar 

  9. Moseley, T., et al.: Identifying potential parallelism via loop-centric profiling. In: Proceedings of the 4th international conference on Computing frontiers, pp. 143–152 (2007)

    Google Scholar 

  10. von Praun, C., Bordawekar, R., Cascaval, C.: Modeling optimistic concurrency using quantitative dependence analysis. In: Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming, pp. 185–196 (2008)

    Google Scholar 

  11. Sato, Y., Inoguchi, Y., Nakamura, T.: On-the-fly detection of precise loop nests across procedures on a dynamic binary translation system. In: 2011 ACM International Conference on Computing Frontiers (2011)

    Google Scholar 

  12. Tiwari, A., et al.: A scalable auto-tuning framework for compiler optimization. In: Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing, pp. 1–12 (2009)

    Google Scholar 

  13. Wu, P., Kejariwal, A., Caşcaval, C.: Compiler-driven dependence profiling to guide program parallelization. In: Languages and Compilers for Parallel Computing: 21th International Workshop, LCPC 2008, pp. 232–248 (2008)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Yukinori Sato .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2011 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Sato, Y. (2011). HPC Systems at JAIST and Development of Dynamic Loop Monitoring Tools Toward Runtime Parallelization. In: Resch, M., Wang, X., Bez, W., Focht, E., Kobayashi, H., Roller, S. (eds) High Performance Computing on Vector Systems 2011. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-22244-3_5

Download citation

Publish with us

Policies and ethics