HPPC 2010: Forth Workshop on Highly Parallel Processing on a Chip

Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6586)


In response to the stagnant growth in conventional, single-processor performance increased on-chip parallelism is seen as a solution to the demands for high performance and power efficiency for general purpose, mainstream computing. While many general-purpose architectures with a moderate number of processing cores are already on the market, architectures with much more significant on-chip parallelism are generally expected, as is already seen for many special purpose processors. How the processing power of such many-core systems can be leveraged for general purpose computing is a most critical and completely open issue, as witnessed by the lack of convergence towards standard architecture and programming models. A major challenge for the coming years therefore is the design of highly parallel single-chip architectures that can support manageable programming abstractions to allow the mainstream programmer to take advantage of the processing power furthered by the technological developments.


Processing Power Parallel Programming Model Standard Architecture Workshop Organizer General Purpose Computing 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  1. 1.VTT – Technical Research Centre of FinlandOuluFinland
  2. 2.Faculty of Computer Science, Department of Scientific ComputingUniversity of ViennaViennaAustria

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