Abstract
IEEE Std 1500 defines a modular and scalable test interface for embedded cores of a system-on-chip (SoC) which simplify test challenges. In this paper, we present a specialized wrapper compatible with IEEE Std 1500 to implement at-speed testing for embedded memory cores. The proposed embedded memory wrapper (EMW) supports test diagnosis with reasonable area overhead which makes it suitable for memory BIST applications. All required test control signals of EMW is generated on-chip by a single centralized memory Built-In-Self Test (BIST) controller. The BIST controller can be used in a hierarchical test design and implement parallel test to handle multiple test wrappers concurrently. Simulation and synthesis results on a group of embedded memory cores confirm that the proposed wrapper has been effectively reduces the test time and area overhead.
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Songhorzadeh, M., Asli, R.N. (2011). Embedded Memory Wrapper Based on IEEE 1500 Standard. In: Ma, M. (eds) Communication Systems and Information Technology. Lecture Notes in Electrical Engineering, vol 100. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-21762-3_5
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DOI: https://doi.org/10.1007/978-3-642-21762-3_5
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