Abstract
The huge design space of Network-on-Chip raise the need of simulators for NoC to efficiently evaluate the performance and select the optimal architecture. This paper presents a review of research on NoC simulators, differentiates the current approaches into three categories: regular network simulators, dedicated NoC simulators, and full-system simulators. We compares the current NoC simulators according to topologies, routing and switching algorithms, traffic models, and discuss the open issues and developing trends in this field.
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© 2011 Springer-Verlag Berlin Heidelberg
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Gu, H. (2011). A Review of Research on Network-on-Chip Simulator. In: Ma, M. (eds) Communication Systems and Information Technology. Lecture Notes in Electrical Engineering, vol 100. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-21762-3_13
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DOI: https://doi.org/10.1007/978-3-642-21762-3_13
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-21761-6
Online ISBN: 978-3-642-21762-3
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