Optimization of Combinational Logic Circuits Using NAND Gates and Genetic Programming

Abstract

The design of an optimized logic circuit that implements a desired Boolean function is of interest. Optimization can be performed in terms of different objectives. They include optimizing the number of gates, the number of levels, the number of transistors of the circuit, etc. In this paper, we describe an approach using genetic programming to optimize a given Boolean function concerning the above mentioned objectives. Instead of commonly used set of gates, i.e. {AND, OR, NOT, XOR}, we use the universal NAND gates which lead to a faster and more compact circuit. The traditional gate minimization techniques produce simplified expressions in the two standard forms: sum of products (SOP) or product of sums (POS). The SOP form can be transformed to a NAND expression by a routine, but the transformation does not lead to optimized circuit; neither in terms of the number of gates, nor the number of levels. Experimental results show our approach produces better results compared to transforming the SOP form to the NAND expression, with respect to the number of gates, levels and transistors of the circuit.