Design and Evaluation of Variable Stages Pipeline Processor Chip

Abstract

In order to reduce the energy consumption in high performance computing, variable stages pipeline architecture (VSP) is proposed, which improves execution time by dynamically unifying the pipeline stages. The VSP processor adopts a special pipeline register called an LDS-cell (Latch D-flip flop Selector - cell) that unifies the pipeline stages and prevents glitch propagation caused by stage unification under low energy mode. The design and fabrication of the VSP processor chip on a Rohm 0.18μm CMOS process is described and the energy consumption is evaluated. The result indicates the VSP processor can achieve 13% less energy consumption than the conventional approach.