Abstract
The Temporal locality and spatial locality have been repeatedly studied and widely exploited in the computer storage hierarchy. They are crucial principles of cache and buffer. But current spatial locality researches have been confined to a small time scale such as several instruction cycles. The periodic page accesses pattern can be discovered by expanding the time scale to seconds. To reduce the rate of cache and buffer miss is the primary goal of most cache and buffer management algorithms. When the miss is inevitable, the practical solution is to reduce the miss cost. A buffer cache management algorithm (Periodicity and Miss Latency Algorithm, PLC) has been proposed based on the periodic page accesses pattern and page miss cost evaluation. By keeping the pages that cost a lot of instruction cycles to swap in or out in cache/buffer as long as possible, the PLC algorithm has been proved practical and efficient.
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© 2011 Springer-Verlag Berlin Heidelberg
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Hou, F., Zhao, Yl., Wang, Y. (2011). The Page Scheduling Schema Exploiting Periodic Access Pattern. In: Lee, J. (eds) Advanced Electrical and Electronics Engineering. Lecture Notes in Electrical Engineering, vol 87. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-19712-3_47
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DOI: https://doi.org/10.1007/978-3-642-19712-3_47
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-19711-6
Online ISBN: 978-3-642-19712-3
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