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Energy-Optimized On-Chip Networks Using Reconfigurable Shortcut Paths

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Part of the Lecture Notes in Computer Science book series (LNTCS,volume 6566)

Abstract

Topology is an important network attribute that greatly affects the power, performance, cost, and design time/effort of NoCs. In this paper, we propose a novel NoC architecture that can exploit the benefits of both application-specific and regular NoC topologies. To this end, a subset of NoC links bypass the router pipeline stages and directly connect remotely located nodes. This results in an NoC which holds both fixed connections between adjacent nodes and long connections virtually connecting non-adjacent nodes. These shortcut paths are constructed at run-time by employing a simple and fast mechanism composed of two processes: on-chip traffic monitoring and path reconfiguration. The former keeps the track of the changes in the on-chip traffic pattern and detects high-volume communication flows. The latter then adapts the shortcut paths to the current on-chip traffic pattern by constructing shortcut paths between the source and destination nodes of the high-volume communication flows. Supporting the shortcut paths imposes a trivial overhead on the area of a conventional packet-switched router. Experimental results reveal the effectiveness of the proposed technique in reducing the energy consumption and improving the performance of NoCs.

Keywords

  • NoC
  • Topology
  • Energy consumption
  • Performance
  • Reconfiguration
  • Short-cut path

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  • DOI: 10.1007/978-3-642-19137-4_20
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References

  1. Owens, J., Dally, W.J., Ho, R., Jayasimha, D.N., Keckler, S.W., Peh, L.S.: Research challenges for on-chip interconnection networks. IEEE Micro 27, 96–108 (2007)

    CrossRef  Google Scholar 

  2. Benini, L., De Micheli, G.: Networks-on-Chip: a new paradigm for systems on chip design. In: Date on design, pp. 418–419 (2002)

    Google Scholar 

  3. Jantsch, A., Tenhunen, H.: Networks on Chip. Kluwer Academic Publishers, Dordrecht (2003)

    CrossRef  MATH  Google Scholar 

  4. Ogras, U., Marculescu, R.: Application-specific network-on-chip architecture customization via long-range link insertion. In: IEEE/ACM International Symposium on Computer Aided Design, San Jose (2005)

    Google Scholar 

  5. Modarressi, M., Tavakkol, A., Sarbazi-Azad, H.: Virtual Point-to-Point Connections in NoCs. IEEE on Computer-Aided Design for Integrated Circuits and Systems 29, 855–868 (2010)

    CrossRef  Google Scholar 

  6. Modarressi, M., Sarbazi-Azad, H., Arjomand, M.: An SDM-Based Hybrid Packet-Circuit-Switched On-Chip Network. In: DATE, pp. 566–569 (2009)

    Google Scholar 

  7. Marchal, P., Verkest, D., Shickova, A., Catthoor, F., Robert, F., Leroy, A.: Spatial Division Multiplexing: a Novel Approach for Guaranteed Throughput on NoCs. In: CODES+ISSS, pp. 81–86 (2005)

    Google Scholar 

  8. Morgenshtein, A., Kolodny, A., Ginosar, R.: Link Division Multiplexing (LDM) for Network-on-Chip Link. In: 24th IEEE International Symposium on Electrical and Electronics Engineers (2006)

    Google Scholar 

  9. Wolkotte, T., Smit, G.J.M., Rauwerda, G.K., Smit, L.T.: An Energy-Efficient Reconfigurable Circuit Switched Network-on- Chip. In: Reconfigurable Architecture Workshop, RAW (2005)

    Google Scholar 

  10. Gomez, C., Gomez, M.E., Lopez, P., Duato, J.: Exploiting Wiring Resources on Interconnection Network: Increasing Path Diversity. In: PDP, pp. 20–29 (2008)

    Google Scholar 

  11. Dally, W.J., Towles, B.: Principles and practices of interconnection networks. Morgan Kaufmann, San Francisco (2004)

    Google Scholar 

  12. Petrov, P., Orailoglu, A.: Performance and Power Effectiveness in Embedded Processors: Customizable Partitioned Caches. In: IEEE International Symposium on Computer Aided Design of Integrated Circuits and Systems, vol. 20 (2001)

    Google Scholar 

  13. Balfour, J., Dally, W.J.: Design tradeoffs for tiled CMP on-chip networks. In: The International Conference of Supercomputing, pp. 178–189 (2006)

    Google Scholar 

  14. Booksim NoC simulator, http://nocs.stanford.edu/booksim.html

  15. Modarressi, M., Sarbazi-Azad, H., Tavakkol, A.: An Efficient Dynamically Reconfigurable On-chip Network Architecture. In: DAC, pp. 166–169 (2010)

    Google Scholar 

  16. Jerger, N.E., Lipasti, M., Peh, L.: Circuit-Switched Coherence. Computer Architecture Letters 6, 5–8 (2007)

    CrossRef  Google Scholar 

  17. Goossens, K., Dielissen, J., Radulescu, A.: The Æthereal Network on Chip: Concepts, Architectures, and Implementations. Design and Test of Computers 22, 414–421 (2005)

    CrossRef  Google Scholar 

  18. Xmulator NoC Simulator, http://www.xmulator.org

  19. Kahng, A., Li, B., Peh, L., Samadi, K.: ORION 2.0: A Fast and Accurate NoC Power and Area Model for Early-Stage Design Space Exploration. In: DATE, France, pp. 423–428 (2009)

    Google Scholar 

  20. SPLASH-2, http://www.flash.stanford.edu/apps/SPLASH

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Teimouri, N., Modarressi, M., Tavakkol, A., Sarbazi-azad, H. (2011). Energy-Optimized On-Chip Networks Using Reconfigurable Shortcut Paths. In: Berekovic, M., Fornaciari, W., Brinkschulte, U., Silvano, C. (eds) Architecture of Computing Systems - ARCS 2011. ARCS 2011. Lecture Notes in Computer Science, vol 6566. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-19137-4_20

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  • DOI: https://doi.org/10.1007/978-3-642-19137-4_20

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-19136-7

  • Online ISBN: 978-3-642-19137-4

  • eBook Packages: Computer ScienceComputer Science (R0)