Introduction
The years of happy scaling are over and the fundamental challenges that the semiconductor industry faces at technology and device level will deeply affect the design of the next generations of integrated circuits and systems. The progressive scaling of CMOS transistors to achieve faster devices and higher circuit density has fuelled the phenomenal success of the semiconductor industry captured by Moores famous law [1]. Silicon technology has entered the nano CMOS era with 35nm MOSFETs in mass production in the 45nm technology generation. However, it is widely recognised that the increasing variability in the device characteristics is among the major challenges to scaling and integration for the present and next generation of nano CMOS transistors and circuits. Variability of transistor characteristics has become a major concern associated with CMOS transistors scaling and integration [2], [3]. It already critically affects SRAM scaling [4], and introduces leakage and timing issues in digital logic circuits [5]. The variability is the main factor restricting the scaling of the supply voltage, which for the last four technology generations has remained virtually constant, adding to the looming power crisis.
In this paper we describe advanced Monte Carlo simulation techniques that are used to study statistical variability in contemporary and future CMOS technology generations at the levels of physical transistor simulation, compact model and circuit simulation. First we review the major sources of statistical variability in nano CMOS transistors focusing at the 45nm technology generation and beyond and introduce the advanced 3D statistical physical statistical simulation technology and tools used to forecasts the magnitude of statistical variability. Statistical compact models used to transfer the variability information obtained from the physical simulations into the circuit simulation and design domain are discussed next. Sensitivity analysis allows the selection of optimal statistical compact model sets of parameters. The use of statistical compact models is illustrated in the simulation of SRAM cells.
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Asenov, A. (2011). Advanced Monte Carlo Techniques in the Simulation of CMOS Devices and Circuits. In: Dimov, I., Dimova, S., Kolkovska, N. (eds) Numerical Methods and Applications. NMA 2010. Lecture Notes in Computer Science, vol 6046. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-18466-6_4
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DOI: https://doi.org/10.1007/978-3-642-18466-6_4
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