Skip to main content

Code Transformations for Embedded Reconfigurable Computing Architectures

  • Chapter
  • 1132 Accesses

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 6491))

Abstract

Embedded Systems permeate all aspects of our daily life, from the ubiquitous mobile devices (e.g., PDAs and smart-phones) to play-stations, set-top boxes, household appliances, and in every electronic system, be it large or small (e.g., in cars, wrist-watches). Most embedded systems are characterized by stringent design constraints such as reduced memory and computing capacity, severe power and energy restrictions, weight and space limitations, most importantly, very short life spans and thus strict design cycles. Reconfiguration has emerged as a key technology for embedded systems as it offers the promise of increased system performance and component number reduction. Reconfigurable components can be customized or specialized (even dynamically) to the task at hand, thereby executing specific tasks more efficiently leading to possible reductions of the weight and power. In this article, we introduce and discuss compilation techniques for reconfigurable embedded systems. We present specific compiler techniques focusing on source-level code transformations highlighting their potential and the applicability of generative programming techniques to this compilation domain.

This is a preview of subscription content, log in via an institution.

Buying options

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Hauck, S., DeHon, A.: Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation. Morgan Kaufmann/Elsevier (2008)

    Google Scholar 

  2. Kuon, I., Tessier, R., Rose, J.: FPGA Architecture: Survey and Challenges, in Foundations and Trends in Electronic Design Automation, pp. 135–253 (2008)

    Google Scholar 

  3. El-Ghazawi, T., et al.: The Promise of High-Performance Reconfigurable Computing. Computer 41(2), 69–76 (2008)

    Article  Google Scholar 

  4. Cardoso, J.M.P., Diniz, P.C.: Compilation Techniques for Reconfigurable Architectures. Springer, Heidelberg (2008)

    MATH  Google Scholar 

  5. Cardoso, J.M.P., Diniz, P.C., Weinhardt, M.: Compiling for Reconfigurable Computing: A Survey. ACM Computing Surveys (CSUR) 42(4) (2010)

    Google Scholar 

  6. Gonzalez, R.: Xtensa: a configurable and extensible processor. IEEE Micro. 20(2), 60–70 (2000)

    Article  MathSciNet  Google Scholar 

  7. Gajski, D., et al.: High-level Synthesis: Introduction to Chip and System Design, p. 359. Kluwer Academic Publishers, Dordrecht (1992)

    Book  Google Scholar 

  8. Muchnick, S.: Advanced Compiler Design and Implementation, p. 856. Morgan Kaufmann Publishers Inc., San Francisco (1997)

    Google Scholar 

  9. Wolfe, M.: High Performance Compilers for Parallel Computing. In: Carter, S., Leda, O. (eds.), p. 570. Addison-Wesley Longman Publishing Co., Inc., Amsterdam (1995)

    Google Scholar 

  10. Aho, A., et al.: Compilers: Principles, Techniques, and Tools, 2nd edn. Addison Wesley, Reading (2006)

    Google Scholar 

  11. Micheli, G.: Synthesis and Optimization of Digital Circuits. McGraw Hill, New York (1994)

    Google Scholar 

  12. Vicki, A., et al.: Software pipelining. ACM Computing Surveys (CSUR) 27(3), 367–432 (1995)

    Article  Google Scholar 

  13. Haldar, M., et al.: A System for Synthesizing Optimized FPGA Hardware from MATLAB. In: IEEE/ACM Intl. Conf. on Computer-Aided Design (ICCAD 2001). IEEE Press, San Jose (2001)

    Google Scholar 

  14. Gokhale, M., Stone, J., Gomersall, E.: Co-Synthesis to a Hybrid RISC/FPGA Architecture. Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology 24(2), 165–180 (2000)

    Article  Google Scholar 

  15. Ziegler, H., et al.: Coarse-Grain Pipelining on Multiple FPGA Architectures. In: 10th IEEE Symp. on Field-Programmable Custom Computing Machines (FCCM 2002). IEEE Computer Society Press, Los Alamitos (2002)

    Google Scholar 

  16. Rodrigues, R., Cardoso, J.M.P., Diniz, P.C.: A Data-Driven Approach for Pipelining Sequences of Data-Dependent Loops. In: Proc. of the 15th IEEE Symp. on Field-Programmable Custom Computing Machines (FCCM 2007). IEEE Computer Society Press, Los Alamitos (2007)

    Google Scholar 

  17. Purna, K., Bhatia, D.: Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers. IEEE Trans. on Computers 48(6), 579–590 (1999)

    Article  Google Scholar 

  18. Ouaiss, I., et al.: An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures. In: Proc. 5th Reconfigurable Architectures Workshop (RAW 1998). Springer, Orlando (1998)

    Google Scholar 

  19. Cardoso, J.M.P., Neto, H.C.: An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs. In: IFIP TC10/WG10.5 Tenth Intl. Conf. on Very Large Scale Integration (VLSI 1999). Kluwer Academic Publishers, Lisbon (2000)

    Google Scholar 

  20. Cardoso, J.M.P.: On Combining Temporal Partitioning and Sharing of Functional Units in Compilation for Reconfigurable Architectures. IEEE Trans. on Computers 52(10), 1362–1375 (2003)

    Article  Google Scholar 

  21. Pandey, A., Vemuri, R.: Combined Temporal Partitioning and Scheduling for Reconfigurable Architectures. In: SPIE Photonics East Conference. SPIE - The International Society for Optical Engineering, Boston (1999)

    Google Scholar 

  22. De Micheli, G., Gupta, R.: Hardware/Software Co-Design. Procedings of the IEEE 85(3), 349–365 (1997)

    Article  Google Scholar 

  23. Kastner, R., et al.: Instruction generation for hybrid reconfigurable systems. In: Proc. of the 2001 IEEE/ACM Intl. Conf. on Computer-Aided Design (ICCAD 2001). IEEE Press, San Jose (2001)

    Google Scholar 

  24. Atasu, K., Pozzi, L., Ienne, P.: Automatic application-specific instruction-set extensions under microarchitectural constraints. In: Proc. of the 40th ACM/IEEE Design Automation Conf. (DAC 2003). ACM Press, Anaheim (2003)

    Google Scholar 

  25. Nayak, A., et al.: Precision and Error Analysis of MATLAB Applications During Automated Hardware Synthesis for FPGAs. In: Design, Automation and Test Conf. in Europe (DATE 2001). IEEE Press, Munich (2001)

    Google Scholar 

  26. So, B., Hall, M., Ziegler, H.: Custom Data Layout for Memory Parallelism. In: Intl. Symp. on Code Generation and Optimization (CGO 2004). IEEE Computer Society Press, Palo Alto (2004)

    Google Scholar 

  27. Ziegler, H., Malusare, P., Diniz, P.: Array Replication to Increase Parallelism in Applications Mapped to Configurable Architectures. In: Ayguadé, E., Baumgartner, G., Ramanujam, J., Sadayappan, P. (eds.) LCPC 2005. LNCS, vol. 4339, pp. 62–75. Springer, Heidelberg (2006)

    Chapter  Google Scholar 

  28. Cardoso, J.M.P., Fernandes, J., Monteiro, M.: Adding Aspect-Oriented Features to MATLAB. In: SPLAT! 2006, Software Engineering Properties of Languages and Aspect Technologies, a Workshop Affiliated with AOSD 2006, Germany (2006)

    Google Scholar 

  29. Czarnecki, K., Eisenecker, U.: Generative Programming: Methods, Tools, and Applications. Addison-Wesley Professional, Reading (June 16, 2000)

    Google Scholar 

  30. Cordy, J.: The TXL Source Transformation Language. Science of Computer Prog. 61(3), 190–210 (2006)

    Article  MathSciNet  MATH  Google Scholar 

  31. Balland, E., et al.: Tom: Piggybacking rewriting on java. In: Baader, F. (ed.) RTA 2007. LNCS, vol. 4533, pp. 36–47. Springer, Heidelberg (2007)

    Chapter  Google Scholar 

  32. Bravenboer, M., et al.: Stratego/XT 0.17. A language and toolset for program transformation. Science of Computer Prog. 72(1-2), 52–70 (2008)

    Article  MathSciNet  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2011 Springer-Verlag Berlin Heidelberg

About this chapter

Cite this chapter

Diniz, P.C., Cardoso, J.M.P. (2011). Code Transformations for Embedded Reconfigurable Computing Architectures. In: Fernandes, J.M., Lämmel, R., Visser, J., Saraiva, J. (eds) Generative and Transformational Techniques in Software Engineering III. GTTSE 2009. Lecture Notes in Computer Science, vol 6491. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-18023-1_8

Download citation

  • DOI: https://doi.org/10.1007/978-3-642-18023-1_8

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-18022-4

  • Online ISBN: 978-3-642-18023-1

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics