Abstract
This paper presents a procedure in designing an oscillator-based hardware random number generator (HRNG) which generates highly random bitstreams even under the deterministic noises. The procedure consists of two parts; HRNG design without considering deterministic noises followed by randomness evaluation under deterministic noises. A stochastic behavior model to efficiently decide the design parameters is proposed, and it is validated by measurement of HRNGs fabricated in 65nm CMOS process. The proposed model directly calculates approximate entropy of output without generating bitstream, which make it easier to explore design space. A simulator considering the power supply noise is also developed for evaluation under deterministic noises.
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Amaki, T., Hashimoto, M., Mitsuyama, Y., Onoye, T. (2011). A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling. In: Chung, Y., Yung, M. (eds) Information Security Applications. WISA 2010. Lecture Notes in Computer Science, vol 6513. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-17955-6_8
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DOI: https://doi.org/10.1007/978-3-642-17955-6_8
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