Abstract
The performance of the sequential digital circuit (Speed, Power consumption etc.) depends upon the performance of flip-flop used in the design. ASIC design flows use characterized data of flip-flops for final signoff. Therefore it’s critical to know precisely the accuracy of characterized data with respect to the actual behavior of flip-flops on silicon. An on-chip flip-flop characterization circuit (FCC) has been presented here which gives the accurate estimation of various parameters of flip-flop such as CP-Q Delay, Setup time, Hold time and Power consumption. The system consists of a digital controller and characterization circuit which are based upon configurable oscillator which could be programmed to oscillate in different configurations or could be operated in functional mode for functional verification. The delay values are calculated by processing the value of time period of oscillator in different modes. The system was fabricated in 40nm CMOS technology and the flip-flop parameters are extracted from it.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Nikolic, B., et al.: Improved sense-amplifier-based flip-flop: Design and measurements. IEEE J. Solid-State Circuits 35, 876–884 (2000)
Singh, A.P., Panwar, N.S., et al.: On Silicon Timing Validation of Digital Logic Gates - A Study of Two Generic Methods. In: 25th International Conference on Microelectronics, pp. 424–427 (2006)
Nedovic, N., et al.: A Test Circuit for Measurement of Clocked Storage Element Characteristics. IEEE Journal of Solid State Circuits 39(8) (August 2004)
Rosenberger, F., et al.: Flip-flop Resolving Time Test Circuit. IEEE Journal of Solid State Circuits SC-17 (4) (August 1982)
Veggetti, A., et al.: Random sampling for on-chip characterization of standard-cell propagation delay. In: Fourth International Symposium on Quality Electronic Design, pp. 41–45 (2003)
Weste, N., Eshragian, K.: Principles of CMOS VLSI Design, pp. 317–324. Book Published by Pearson Education Asia
Yuan, J., et al.: New Single-Clock CMOS Latches and Flipflops with improved Speed and Power Savings. IEEE Journal of Solid State Circuits 32(1), 62–69 (1997)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2011 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Jain, A., Veggetti, A., Crippa, D., Rolandi, P. (2011). An On-Chip Flip-Flop Characterization Circuit. In: van Leuken, R., Sicard, G. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. PATMOS 2010. Lecture Notes in Computer Science, vol 6448. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-17752-1_5
Download citation
DOI: https://doi.org/10.1007/978-3-642-17752-1_5
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-17751-4
Online ISBN: 978-3-642-17752-1
eBook Packages: Computer ScienceComputer Science (R0)