Skip to main content

A Power-Aware Online Scheduling Algorithm for Streaming Applications in Embedded MPSoC

  • Conference paper
Book cover Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation (PATMOS 2010)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 6448))

Abstract

As application complexity grows, embedded systems move to multiprocessor architectures to cope with the computation needs. The issue for multiprocessor architectures is to optimize the processing resources usage and power consumption to reach a higher energy efficiency. These optimizations are handled by scheduling techniques. To tackle this issue we propose a global online scheduling algorithm for streaming applications. It takes into account data dependencies between pipeline tasks to optimize processor usage and reduce power consumption through the use of DPM and DVFS modes. An implementation of the algorithm on a virtual platform, executing a WCDMA application, demonstrates up to 45% power consumption gain while guaranteeing regular data throughput.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Venkatachalam, V., Franz, M.: Power Reduction Techniques For Microprocessor Systems. ACM Computing Surveys (CSUR) 37(3), 195–237 (2005)

    Article  Google Scholar 

  2. Intel PXA27x Processor Family, Electrical, Mechanical, and Thermal Specification (2005)

    Google Scholar 

  3. Dertouzos, M.L., Mok, A.K.: Multiprocessor Online Scheduling of Hard-Real-Time Tasks. IEEE Transactions on Software Engineering 15(12), 1497–1506 (1989)

    Article  Google Scholar 

  4. Benini, L., Bertozzi, D., Guerri, A., Milano, M.: Allocation, Scheduling and Voltage Scaling on Energy Aware MPSoCs. In: Beck, J.C., Smith, B.M. (eds.) CPAIOR 2006. LNCS, vol. 3990, pp. 44–58. Springer, Heidelberg (2006)

    Chapter  Google Scholar 

  5. Lu, Y.-H., Benini, L., De Micheli, G.: Dynamic Frequency Scaling with Buffer Insertion for Mixed Workloads. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 21(5), 1284–1305 (2002)

    Google Scholar 

  6. Pettis, N., Cai, L., Lu, Y.-H.: Statistically Optimal Dynamic Power Management for Streaming Data. IEEE Transactions on Computers 55(7), 800–814 (2006)

    Article  Google Scholar 

  7. Kim, K.H., Buyya, R., Kim, J.: Power Aware Scheduling of Bag-of-Tasks Applications with Deadline Constraints on DVS-enabled Clusters. In: IEEE International Symposium on Cluster Computing and the Grid (CCGRID), pp. 541–548 (2007)

    Google Scholar 

  8. Zhang, F., Chanson, S.T.: Power-Aware Processor Scheduling under Average Delay Constraints. In: IEEE Real Time on Embedded Technology and Applications Symposium (RTAS), pp. 202–212 (2005)

    Google Scholar 

  9. Choudhury, P., Chakrabarti, P.P., Kumar, R.: Online Dynamic Voltage Scaling using Task Graph Mapping Analysis for Multiprocessors. In: International Conference on VLSI Design (VLSID), pp. 89–94 (2007)

    Google Scholar 

  10. Hua, S., Qu, G., Bhattacharyya, S.S.: Energy-Efficient Embedded Software Implementation on Multiprocessor System-on-Chip with Multiple Voltages. ACM Transactions on Embedded Computing Systems (TECS) 5(2), 321–341 (2006)

    Article  Google Scholar 

  11. Zhang, F., Chanson, S.T.: Blocking-Aware Processor Voltage Scheduling for Real-Time Tasks. ACM TECS 3(2), 307–335 (2004)

    Article  Google Scholar 

  12. Im, C., Kim, H., Ha, S.: Dynamic Voltage Scheduling Technique for Low-Power Multimedia Applications Using Buffers. In: ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 34–39 (2001)

    Google Scholar 

  13. Ventroux, N., Guerre, A., Sassolas, T., Moutaoukil, L., Bechara, C., David, R.: SESAM: an MPSoC Simulation Environment for Dynamic Application Processing. In: IEEE International Conference on Embedded Software and Systems, ICESS (2010)

    Google Scholar 

  14. Guerre, A., Ventroux, N., David, R., Merigot, A.: Approximate-Timed Transactional Level Modeling for MPSoC Exploration: A Network-on-Chip Case Study. In: IEEE Euromicro Symposium on Digital Systems Design (DSD), pp. 390–397 (2009)

    Google Scholar 

  15. Richardson, A.: WCDMA Design Handbook (2006)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2011 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Sassolas, T., Ventroux, N., Boudouani, N., Blanc, G. (2011). A Power-Aware Online Scheduling Algorithm for Streaming Applications in Embedded MPSoC. In: van Leuken, R., Sicard, G. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. PATMOS 2010. Lecture Notes in Computer Science, vol 6448. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-17752-1_1

Download citation

  • DOI: https://doi.org/10.1007/978-3-642-17752-1_1

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-17751-4

  • Online ISBN: 978-3-642-17752-1

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics