Asynchronous Parallel Logic Simulation on Modern Graphics Processors

  • Yangdong Deng
  • Yuhao Zhu
  • Wang Bo
Part of the Lecture Notes in Earth System Sciences book series (LNESS)


Logic simulation has become the bottleneck of today’s integrated circuit (IC) design projects. For instance, over 80 % of the IC design turn-around time of NVIDIA is spent on logic simulation even with NVIDIA’s proprietary supercomputing facility. It is thus essential to develop parallel simulation solutions to maintain the momentum of increasing IC integration capacity. Inspired by the supreme parallel computing power of modern GPUs, in this chapter we reported our recent work on using GPU to accelerate the time-consuming IC verification process by developing a massively parallel gate-level logical simulator. To the best of authors’ knowledge, this work is the first one to leverage the power of the modern GPUs to successfully unleash the massive parallelism of a conservative discrete event driven algorithm, CMB algorithm. Based on a novel data-parallel algorithmic mapping strategy, both the data structure and processing flow of the CMB protocol are re-designed to better exploit the potential of modern GPUs. A dynamic memory management mechanism is developed to efficiently utilize the relatively limited GPU memory resource. Experimental results prove that our GPU based simulator outperforms a CPU baseline event-driven simulator by a factor of 47.4X on average. This work demonstrates that the CMB algorithm can be efficiently and effectively deployed on GPUs without the performance overhead that had hindered its successful applications on previous parallel architectures.


Priority Queue Event Queue Logic Simulation Modern GPUs Data Level Parallelism 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Yangdong Deng
    • 1
  • Yuhao Zhu
    • 2
  • Wang Bo
    • 3
  1. 1.Institute of MicroelectronicsTsinghua UniversityBeijingChina
  2. 2.Department of Computer ScienceUniversity of TexasAustinUSA
  3. 3.Department of Electrical EngineeringStanford UniversityStanfordUSA

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