Abstract
This paper proposes a high-speed multi-diameter CNFET-based 7T (seven transistor) SRAM (static random access memory) cell. It investigates the impact of process, voltage and temperature (PVT) variations on its design metrics and compares the results with its counterpart – CMOS-based 7T SRAM cell. The proposed design offers 77.4× improvement in write access time along with 88.1× reduction in write access time variation and 117.8× saving in write power along with substantial reduction in write EDP/write EDP variation. The proposed memory cell shows 40% improvement in SNM (static noise margin) and better robustness against PVT variations.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Duvall, S.G.: Statistical circuit modeling and optimization. In: 5th Intl. Workshop on Statistical Metrology, pp. 56–63 (2000)
Eisele, M., Berthold, J., Schmitt-Landsiedel, D., Mahnkopf, R.: The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits. In: Proc. ISLPED 1996, pp. 237–242 (1996)
Burnett, D., Erington, K., Subramanian, C., Baker, K.: Implications of fundamental threshold voltage variations for high-density SRAM and logic circuits. In: Proc. Symp. VLSI Tech., pp. 15–16 (1994)
Rusu, S., Tam, S., Muljono, H., Ayers, D., Chang, J., Cherkauer, B., Stinson, J., Benoit, J., Varada, R., Leung, J.: A 65-nm Dual-Core Multithreaded Xeon Processor With 16-MB L3 Cache. IEEE Journal of Solid-State Circuits (2007)
Alam, M., Kang, K., Paul, B.C., Roy, K.: Reliability and Process –Variation Aware Design of VLSI Circuits. In: Proceedings of 14th IPFA 2007, Bangalore, India (2007)
Stanford University CNFET Model Web site (2008), http://nano.stanford.edu/model.php?id=23
Deng, J., Wong, H.-S.P.: A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application - Part I: Model of the Intrinsic Channel Region. IEEE Trans. Electron Devices 54, 3186–3194 (2007)
Deng, J., Wong, H.-S.P.: A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application - Part II: Full Device Model and Circuit Performance Benchmarking. IEEE Trans. Electron Devices 54, 3195–3205 (2007)
Aly, R., Faisal, M., Bayoumi, A.: Novel 7T SRAM cell for low power cache design. In: Proc. IEEE SOC Conf., pp. 171–174 (2005)
Berkeley Predictive Technology Model, UC Berkeley Device Group, http://www-device.eecs.berkeley.edu/~ptm/
Calhoun, B.H., Chandrakasan, A.P.: Static Noise Margin Variation for Sub-threshold SRAM in 65-nm CMOS. IEEE Journal of Solid State Circuits 42(7) (2006)
Rabaey, J.M.: Digital Integrated Circuits: A Design Perspective. Prentice-Hall, Englewood Cliffs (1996)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2010 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Islam, A., Hasan, M. (2010). High Speed Cache Design Using Multi-diameter CNFET at 32nm Technology. In: Das, V.V., Vijaykumar, R. (eds) Information and Communication Technologies. ICT 2010. Communications in Computer and Information Science, vol 101. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-15766-0_31
Download citation
DOI: https://doi.org/10.1007/978-3-642-15766-0_31
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-15765-3
Online ISBN: 978-3-642-15766-0
eBook Packages: Computer ScienceComputer Science (R0)