Characterizing the Impact of Using Spare-Cores on Application Performance

  • José Carlos Sancho
  • Darren J. Kerbyson
  • Michael Lang
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6271)


Increased parallelism on a single processor is driving improvements in peak-performance at both the node and system levels. However achievable performance, in particular from production scientific applications, is not always directly proportional to the core count. Performance is often limited by constraints in the memory hierarchy and also by a node inter-connectivity. Even on state-of-the-art processors, containing between four and eight cores, many applications cannot take full advantage of the compute-performance of all cores. This trend is expected to increase on future processors as the core count per processor increases. In this work we characterize the use of spare-cores, cores that do not provide any improvements in application performance, on current multi-core processors. By using a pulse-width modulation method, we examine the possible performance profile of using a spare-core and quantify under what situations its use will not impact application performance. We show that, for current AMD and Intel multi-core processors, spare-cores can be used for substantial computational tasks but can impact application performance when using shared caches or when significantly accessing main memory.


Main Memory Pulse Width Modulation Application Performance Multicore Processor Through Silicon Vias 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2010

Authors and Affiliations

  • José Carlos Sancho
    • 1
  • Darren J. Kerbyson
    • 2
  • Michael Lang
    • 3
  1. 1.Barcelona Supercomputing CenterBarcelonaSpain
  2. 2.Pacific Northwest National LaboratoryRichlandUSA
  3. 3.Los Alamos National LaboratoryLos AlamosUSA

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