An Operational Model for Multiprocessors with Caches
Modern multiprocessors are equipped with local caches, to enhance program performance. However, the presence of caches can lead to the violation of sequential consistency  assumptions regarding program order and write atomicity. With respect to such relaxed memory models , we provide an operational description of program execution (in the style of ) that accounts for cache effects. In particular, we provide an operational characterization of cache invalidation and update policies and an abstract characterization of cache consistency. The programming model consists of a simple imperative language extended with common synchronization primitives such as locks or barrier instructions. The main results show that by precluding certain data races or by placing certain synchronization constraints, sequentially consistent behavior can be obtained for multiprocessor execution even in the presence of local caches.
KeywordsSystem Transition Memory Model Local Cache Cache Replacement Data Race
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