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Packaging Trends and Technology in Wireless and SSD Applications

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Abstract

Hand-handled, wireless world represents the most challenging environment for package technology where all the system performances must be densely stacked. Chip scale package (CSP) is the generic term for packages approaching chip size, and the fine-pitch versions of BGA have become the most widely used kind of CSP for system miniaturization. With the introduction of the new feature, where heterogeneous semiconductor devices are stacked together within a single package working at extremely high frequencies, the package design in terms of system simulation – mechanical, electrical, and thermal – is becoming one of most important development activities for delivering robust system solutions. In this chapter, the package historical trends against the system evolution will be discussed, analyzing the principal integration challenging. Among them, this chapter will focus on thin die thickness trend, taking into account the new process technology and the related impact on the device characteristics. This is considered as one of the most important back-end technologies, enabling the new era of the package integration and miniaturization. New interconnection technologies among dies will also be reviewed and discussed by deeply analyzing the features of through silicon via process. This process will allow the new interconnection scheme for microelectronics for the next decade.

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References

  1. Gaulhofer E, Oyrer H (2000) Semicon Singapore 2000, May 09–11

    Google Scholar 

  2. Landesberger C, Klink G, Schwinn G, Aschenbrenner R (March 2001) Advanced packaging materials, processes, properties and interfaces. In Proceedings of IEEE 01TH8562, ISBN 0-930815-64-5, pp 92–97

    Google Scholar 

  3. Liu JH, Pei ZJ, Fisher GR (2007) Int J Mach Tools Manufact 47(1):1–13

    Article  Google Scholar 

  4. McGuire K, Danyluk S, Baker TL, Rupnow JW, McLaughlin D (1997) J Mater Sci 32:1017–1024

    Article  Google Scholar 

  5. Chen J, De I (2003) Wolf Semicond Sci Technol 18:261–268

    Article  Google Scholar 

  6. Landesberger C, Scherbaum S, Schwinn G, Spöhrle H (2001) In Proceedings of microsystems technologies. Mesago, Stuttgart, pp 431–436

    Google Scholar 

  7. Sibailly O, Wagner F, Richerzhagen B (2004) Future. Fab Intl (16):146–147

    Google Scholar 

  8. Perrottet D, Buchilly JM, Wagner F, Richerzhagen B (August 2004) Semiconductor manufacturing. pp 46–50

    Google Scholar 

  9. Schmitz TL, Davies A, Evans CJ (2003) American Society for Precision Engineering (ASPE). Winter Topical Meet 28:98–103

    Google Scholar 

  10. Ali YM, Zhang LC (1999) J Mater Process Technol 89–90:561–568

    Article  Google Scholar 

  11. Alberici S, Dellafiore A, Manzo G, Santospirito G, Villa CM, Zanotti L (2004) Microelectronic Eng 76:227–234

    Article  Google Scholar 

  12. Alberici S, Coulon D, Joubin P, Mignot Y, Oggioni L, Petruzza P, Piumi D, Zanotti L (2003) Microelectronic Eng 70:558–565

    Article  Google Scholar 

  13. Zulehner W, Huber D (1982) Czochralsky-grown silicon. Crystals 8:1–143

    Google Scholar 

  14. Wilkes J G (1983) The precipitation of oxygen in silicon. J Crystal Growth 65:214–230

    Article  Google Scholar 

  15. Borghesi A, Pivac B, Sassella A, Stella S (1995) Oxygen precipitation in silicon. Appl Phys Rev 77:4169–4244

    Article  Google Scholar 

  16. Tan TY, Gardner EE, Tice WK (1977) Intrinsic gettering by oxygen precipitate induced dislocations in Czochralski Silicon. Appl Phys Lett 30:175–176

    Article  Google Scholar 

  17. Murray EM (1984) Denuded zone formation in p silicon. J Appl Phys 55:536–541

    Article  Google Scholar 

  18. Yamamoto K, Kishino S, Matsushita Y, Iizuka T (1980) Lifetime improvement in Czochralski-grown silicon wafers by the use of a two-step annealing. Appl Phys Lett 6:195–197

    Article  Google Scholar 

  19. Polignano ML, Brambilla M, Cazzaniga F, Pavia G, Zanderigo F (1998) Denuded zone thickness from surface photovoltage measurements: comparison with microscopy techniques. J Electrochem Soc 145:1632–1639

    Article  Google Scholar 

  20. Falster R, Gambaro D, Olmo M, Cornara M, Korb H (1998) The engineering of silicon wafer material properties through vacancy concentration profile control and the achievement of ideal oxygen precipitation behaviour. Mat Res Soc Symp Proc 510:27–35

    Google Scholar 

  21. Falster R, Cornara M, Gambaro D, Olmo M (1999) Ideal oxygen precipitating silicon wafers and oxygen out-diffusion-less process. US patent US 5994761

    Google Scholar 

  22. Nakai K, Inoue Y, Yokota H, Ikari A, Takahashi J, Tachikawa A, Kitahara K, Ohta Y, Ohashi W (2001) Oxygen precipitation in nitrogen-doped Czochralski-grown silicon crystals. J Appl Phys 89:4301–4309

    Article  Google Scholar 

  23. von Ammon W, Dreier P, Hensel W, Lambert U, Köster L (1996) Influence of oxygen and nitrogen on point defect aggregation in silicon single crystals. Mat Sci Eng B 36:33–41

    Article  Google Scholar 

  24. von Ammon W, Hölzl R, Virbulis J, Dornberger E, Schmolke R, Gräf D (2001) The impact of nitrogen on the defect aggregation in silicon. J Crystal Growth 226:19–30

    Article  Google Scholar 

  25. Graf K (2000) Metal impurities in silicon device fabrication. Springer, Berlin

    Google Scholar 

  26. Polignano ML, Brivio J, Codegoni D, Grasso S, Altmann R, Nutsch A (2009) Revealing copper contamination in silicon after low temperature treatments. Electrochem Soc Trans 25:337–348

    Google Scholar 

  27. Zerbst M (1966) Relaxation effects at semiconductor-insulator interfaces. Z Angew Phys 22:30–33

    Google Scholar 

  28. Kang JS, Schröder DK (1985) The pulsed MIS capacitor – a critical review. Phys Stat Sol (a) 89:13–43

    Article  Google Scholar 

  29. Beckhoff B, Nutsch A, Altmann R, Borionetti G, Pello C, Polignano ML, Codegoni D, Grasso S, Cazzini E, Bersani M, Lazzeri P, Gennaro S, Kolbe M, Muller M (2009) Highly sensitive detection of inorganic contamination. Solid State Phenomena 145–146:101–104

    Article  Google Scholar 

  30. Dishman JM, Haszko SE, Marcus RB, Murarka SP, Sheng TT (1979) Electrically active stacking faults in CMOS integrated circuits. J Appl Phys 50:2689–2696

    Article  Google Scholar 

  31. Falster R (1989) Gettering in silicon by oxygen related defects, stacking faults and thin polycrystalline films. Solid State Phenomena 6–7:13–20

    Article  Google Scholar 

  32. Vanhellemont J, Claeys C (1988) Intrinsic gettering: sense or nonsense? In: Soncini G, Calzolari PU (eds) Proceedings of ESSDERC ’87. North Holland, Amsterdam, pp 451–454

    Google Scholar 

  33. Falster R, Bergholz W (1990) The gettering of transition metals by oxygen-related defects in silicon. J Electrochem Soc 137:1548–1559

    Article  Google Scholar 

  34. Hwang JM, Schroder DK (1986) Recombination properties of oxygen precipitated silicon. J Appl Phys 59, 2476–2487

    Article  Google Scholar 

  35. Porrini M, Gambaro D, Gerenzani P, Falster R (1996) Influence of oxygen and oxygen-related defects on the minority carrier lifetime of high purity CZ and MCZ silicon. Electrochem Soc Proc 96–13:170–179

    Google Scholar 

  36. Pang SK, Rohatgi A, Sopori BL, Fiegl G (1990) A comparison of minority carrier lifetime in as-grown and oxidized float-zone, magnetic Czochralski and Czochralski silicon. J Electrochem Soc 137:1977–1981

    Article  Google Scholar 

  37. Jastrzebski L (1989) Heavy metal contamination during integrated-circuit processing: measurements of contamination level and internal gettering efficiency by surface photovoltage. Mat Sci Eng B4:113–121

    Google Scholar 

  38. Jastrzebski L, Henley W, Nuese CJ (1992) Surface photovoltage monitoring of heavy metal contamination in IC manufacturing. Solid-State Technol 35:27–33

    Article  Google Scholar 

  39. Goodman AM (1961) A method for the measurement of short minority carrier diffusion lengths in semiconductors. J Appl Phys 32 :2550–2552

    Article  Google Scholar 

  40. Clendenin M (November 2006) Samsung wraps up 16 NAND die in multi-chip package. EE Times Europe. http://www.eetimes.eu/193500880

  41. IBM Press Release (April 2007) http://www-03.ibm.com/press/us/en/index.wss

  42. Schmidt RR, Notohardjono BD (2002) High-end server low-temperature cooling. IBM J Res Dev 46(6):739–752

    Article  Google Scholar 

  43. Joseph J, Gillis JD, Doherty M, Lindgren PJ, Previti-Kelly RA, Malladi RM, Wang P-C et al (2008) Through-silicon vias enable next-generation SiGe power amplifiers for wireless communications. IBM J Res Dev 52(6):635–648

    Article  Google Scholar 

  44. Andry P, Tsang C, Sprogis E, Patel C, Wright S, Webb B (May 30–June 2, 2006) A CMOS-compatible process for fabricating electrical through-vias in silicon. In Proceedings of the 56th Electronic Components and Technology Conference, pp 831–837

    Google Scholar 

  45. Takahaski K, Taguchi Y, Tomisaka M, Yonemara H, Hoshino M, Ueno M, Egawa Y, et al (June 1–4, 2004) Process integration of 3D chip stack with vertical interconnection. In Proceedings of the 54th Electronic Components and Technology Conference, pp 601–609

    Google Scholar 

  46. Knickerbocher et al (November 2008) IBM J Res Dev 52(6):553

    Google Scholar 

  47. Zhang J et al (November 2006) IEEE Trans Semicond Manufact 19(4):437

    Google Scholar 

  48. Läermer F, Schilp P, Bosch Gmbh R (1996) Method of anisotropically etching silicon. U.S. Patent 5501893

    Google Scholar 

  49. Henry D et al (May 2008) Through silicon vias technology for CMOS image sensors packaging. In Proceedings of the 58th Electronic Components and Technology Conference, pp 556–562

    Google Scholar 

  50. Joseph et al (November 2008) IBM J Res Dev 52(6):635

    Article  Google Scholar 

  51. Shaper et al (August 2005) IEEE Trans Adv Packag 28(3):356

    Article  Google Scholar 

  52. Abhulimen et al (Nov/Dec 2008) J Vac Sci Technol B 26(6)

    Google Scholar 

  53. Kim B (2007) Mater Res Soc Symp Proc 970 © 2007 Mater Res Soc 0970-Y06-02

    Google Scholar 

  54. Andry PS et al (November 2008) IBM J Res Dev 52(6):571

    Article  Google Scholar 

  55. Laviron C et al (2009) In Proceedings of the 59th Electronic Components and Technology Conference, pp 14–19

    Google Scholar 

  56. Chen DY (2009) Enabling 3D-IC foundry technologies for 28 nm node and beyond: through-silicon-via integration with high throughput die-to-wafer stacking, IEDM 09, Maryland, USA

    Google Scholar 

  57. Tanaka (2002) In Proceedings of the 52nd Electronic Component and Technology Conference

    Google Scholar 

  58. Tanaka (2003) In Proceedings of the 53rd Electronic Component and Technology Conference

    Google Scholar 

  59. Takahashi (2003) Microelctr Reliabil 43:1267–1279

    Article  Google Scholar 

  60. Morrow P (May 2006) IEEE Electr Dev Lett 27(5):335

    Article  MathSciNet  Google Scholar 

  61. Wieland R (December 2005) Microelectronic engineering in Proceedings of the 9th European Workshop on Materials for Advanced Metallization 82(3–4):529–533.

    Google Scholar 

  62. Katti G 3D stacked ICs using Cu TSVs and die to wafer hybrid collective bonding, IEDM09

    Google Scholar 

  63. (2008) Handbook of 3D integration. Wiley-VCH, p 688

    Google Scholar 

Download references

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Correspondence to Aldo Losavio .

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Losavio, A., Codegoni, D., Polignano, M.L., Zanderigo, F., Zanotti, L. (2011). Packaging Trends and Technology in Wireless and SSD Applications. In: Campardo, G., Tiziani, F., Iaculo, M. (eds) Memory Mass Storage. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-14752-4_6

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  • DOI: https://doi.org/10.1007/978-3-642-14752-4_6

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