Real-Time Biologically-Inspired Image Exposure Correction

  • Vassilios Vonikakis
  • Chryssanthi Iakovidou
  • Ioannis Andreadis
Part of the IFIP Advances in Information and Communication Technology book series (IFIPAICT, volume 313)


This chapter presents a real-time FPGA implementation of a biologically-inspired image enhancement algorithm. The algorithm compensates for the under/over-exposed image regions, emerging when High Dynamic Range (HDR) scenes are captured by contemporary imaging devices. The transformations of the original algorithm, which are necessary in order to meet the requirements of an FPGA-based hardware system, are presented in detail. The proposed implementation, which is synthesized in Altera’s Stratix II GX: EP2SGX130GF1508C5 FPGA device, features pipeline architecture, allowing the real-time rendering of color video sequences (25fps) with frame sizes up to 2.5Mpixels.


FPGA Real-Time Image Enhancement Human Visual System High Dynamic Range Imaging 


  1. 1.
    Battiato, S., Castorina, A., Mancuso, M.: High Dynamic Range Imaging for Digital Still Camera: an overview. Journal of Electronic Imaging 12, 459–469 (2003)CrossRefGoogle Scholar
  2. 2.
    Jobson, D., Rahman, Z., Woodell, G.: A Multi-scale Retinex for Bridging the Gap between Color Images and the Human Observation of Scenes. IEEE Transactions Image Processing 6, 965–976 (1997)CrossRefGoogle Scholar
  3. 3.
    Kimmel, R., Elad, M., Shaked, D., Keshet, R., Sobel, I.: A Variational Framework for Retinex. International Journal of Computer Vision 52, 7–23 (2003)zbMATHCrossRefGoogle Scholar
  4. 4.
    Hines, G., Rahman, Z., Jobson, D., Woodell, G.: DSP Implementation of the Retinex Image Enhancement Algorithm. In: Proceedings of the SPIE 5438: Visual Information Processing XIII, pp. 13–24 (2004)Google Scholar
  5. 5.
    Hines, G., Rahman, Z., Jobson, D., Woodell, G., Harrah, S.: Real-time Enhanced Vision System. In: Proceedings of the SPIE 5802: Enhanced and Synthetic Vision, pp. 127–134 (2005)Google Scholar
  6. 6.
    Seponara, S., Fanucci, L., Marsi, S., Ramponi, G.: Algorithmic and Architectural Design for Real-time and Power-efficient Retinex Image/Video Processing. Journal of Real-Time Image Processing 1, 267–283 (2007)CrossRefGoogle Scholar
  7. 7.
    Vonikakis, V., Andreadis, I., Gasteratos, A.: Fast Centre-surround Contrast Modification. IET Image Processing 2(1), 19–34 (2008)CrossRefGoogle Scholar
  8. 8.
    Benedetti, A.: Image Convolution on FPGAs: the Implementation of a Multi-FPGA FIFO structure. EUROMICRO 1, 123–130 (1998)MathSciNetGoogle Scholar

Copyright information

© IFIP 2010

Authors and Affiliations

  • Vassilios Vonikakis
    • 1
  • Chryssanthi Iakovidou
    • 1
  • Ioannis Andreadis
    • 1
  1. 1.Department of Electrical & Computer Engineering Laboratory of ElectronicsDemocritus University of ThraceXanthiGreece

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