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Fast Instruction Memory Hierarchy Power Exploration for Embedded Systems

  • Nikolaos Kroupis
  • Dimitrios Soudris
Part of the IFIP Advances in Information and Communication Technology book series (IFIPAICT, volume 313)

Abstract

A typical instruction memory design exploration process using simulation tools for various cache parameters is a rather time-consuming process, even for low complexity applications. In order to design a power efficient memory hierarchy of an embedded system, a huge number of system simulations are needed for all the different instruction memory hierarchies, because many cache memory parameters should be explored. Exhaustive search of design space using simulation is too slow procedure and needs hundreds of simulations to find the optimal cache configuration. This chapter provides fast and accurate estimates of a multi-level instruction memory hierarchy. Using a detail methodology for estimating the number of instruction cache misses of the instruction cache levels and power models; we estimate within a reasonable time the power consumption among these hierarchies. In order to automate the estimation procedure, a novel software tool named FICA implements the proposed methodology, which automatically estimates the total energy in instruction memory hierarchy and reports the optimal one.

Keywords

Cache Size Memory Hierarchy Cache Memory Control Flow Graph Assembly Code 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    Segars, S.: Low power design techniques for micro-processors. In: International Solid State Circuit Conference (February 2001)Google Scholar
  2. 2.
    Zhang, D., Vahid, F.: Cache configuration exploration on prototyping platforms. In: 14th IEEE International Workshop on Rapid System Prototyping, June 2003, pp. 164–170 (2003)Google Scholar
  3. 3.
    Silva-Filho, A.G., et al.: Heuristic for Two-Level Cache Hierarchy Exploration Considering Energy Consumption and Performance. In: Vounckx, J., Azémard, N., Maurine, P. (eds.) PATMOS 2006. LNCS, vol. 4148, pp. 75–83. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  4. 4.
    Gordon-Ross, A., Vahid, F., Dutt, N.: Automatic Tuning of Two-Level Caches to Embedded Applications. In: Design, Automation and Test in Europe, DATE, February 2004, pp. 208–213 (2004)Google Scholar
  5. 5.
    Givargis, T., Vahid, F.: Platune: A Tuning framework for system-on-a-chip platforms. IEEE Trans. Computer-Aided Design 21, 1–11 (2002)CrossRefGoogle Scholar
  6. 6.
    Borg, A., Kessler, R., Wall, D.: Generation and analysis of very long address traces. In: International Symposium on Computer Architecture, May 1990, pp. 270–279 (1990)Google Scholar
  7. 7.
    Mueller, F., Whalley, D.: Fast Instruction Cache Analysis via Static Cache Simulation. In: Proc. of 28th Annual Simulation Symposium, pp. 105–114 (1995)Google Scholar
  8. 8.
    Lajolo, M., Lavagno, L., Sangiovanni-Vincentelli, A.: Fast instruction cache simulation strategies in a hardware/software co-design environment. In: Proc. of the Asian and South Pacific Design Automation Conference, ASP-DAC 1999 (January 1999)Google Scholar
  9. 9.
    Nohl, A., Braun, G., Schliebusch, O., Leupers, R., Meyr, H.: A Universal Technique for Fast and Flexible Instruction-Set Architecture Simulation. In: Proc. of the 39th conference on Design automation, DAC 2002, New Orleans, Louisiana, USA, pp. 22–27 (2002)Google Scholar
  10. 10.
    Hoffmann, A., Kogel, T., Nohl, A., Braun, G., Schliebusch, O., Wieferink, A., Meyr, H.: A Novel Methodology for the Design of Application Specific Instruction Set Processors (ASIP) Using a Machine Description Language. IEEE Transactions on Computer-Aided Design 20(11), 1338–1354 (2001)CrossRefGoogle Scholar
  11. 11.
    Balaji, R.: Fast Design Space Exploration of Instruction Caches. Msc Thesis, National University of Singapore (2003)Google Scholar
  12. 12.
    Kroupis, N., Mamagkakis, S., Soudris, D.: An Estimation Methodology for Designing Instruction Cache Memory of Embedded Systems. In: ESTIMedia 2006, Fourth IEEE Workshop on Embedded Systems for Real Time Multimedia, Seoul, Korea, October 26-27 (2006)Google Scholar
  13. 13.
    Liveris, N., Zervas, N., Soudris, D., Goutis, C.: A Code Transformation-Based Methodology for Improving I-Cache Performance of DSP Applications. In: Proc. of DATE, Paris, pp. 977–984 (2002)Google Scholar
  14. 14.
    Tarjan, D., Shyamkumar, T., Jouppi, N.: CACTI 4.0 HPL Tech. Report HPL-2006-86 (June 2006)Google Scholar
  15. 15.
    Calculating Memory System Power for DDR2, Technical Note, Micron Technology Inc. (2007)Google Scholar
  16. 16.
    Austin, T., Larson, E., Ernst, D.: SimpleScalar: An Infrastructure for Computer System Modeling. Computer 35(2), 59–67 (2002)CrossRefGoogle Scholar
  17. 17.
    Kuhn, P.: Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation. Kluwer Academic Publisher, Boston (1999)MATHGoogle Scholar
  18. 18.
    Nam, K., et al.: A fast hierarchical motion vector estimation algorithm using mean pyramid. IEEE Transactions on Circuits and Systems for Video Technology 5(4), 344–351 (1995)CrossRefGoogle Scholar
  19. 19.
    Cheung, C.-K., Po, L.-M.: Normalized Partial Distortion Search Algorithm for Block Motion Estimation. Proc. IEEE Transaction on Circuits and Systems for Video Technology 10(3), 417–422 (2000)Google Scholar
  20. 20.
    Lafruit, G., Nachtergaele, L., Vahnhoof, B., Catthoor, F.: The Local Wavelet Transform: A Memory-Efficient, High-Speed Architecture Optimized to a Region-Oriented Zero-Tree Coder. Integrated Computer-Aided Engineering 7(2), 89–103 (2000)Google Scholar
  21. 21.
    Danckaert, K., Catthoor, F., De Man, H.: Platform independent data transfer and storage exploration illustrated on a parallel cavity detection algorithm. In: ACM Conference on Parallel and Distributed Processing Techniques and Applications III, pp. 1669–1675 (1999)Google Scholar
  22. 22.
    Dekker, A.: Kohonen neural networks for optimal colour quantization. Network: Computation in Neural Systems 5, 351–367 (1994)MATHCrossRefGoogle Scholar

Copyright information

© IFIP 2010

Authors and Affiliations

  • Nikolaos Kroupis
    • 1
  • Dimitrios Soudris
    • 2
  1. 1.Department of Information and Telecommunication TechnologyTechnological Institute of LarisaLarisaGreece
  2. 2.School of Electrical & Computer Engineering, Department of Computer ScienceNational Technical University of AthensAthensGreece

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