Fast Instruction Memory Hierarchy Power Exploration for Embedded Systems

  • Nikolaos Kroupis
  • Dimitrios Soudris
Part of the IFIP Advances in Information and Communication Technology book series (IFIPAICT, volume 313)


A typical instruction memory design exploration process using simulation tools for various cache parameters is a rather time-consuming process, even for low complexity applications. In order to design a power efficient memory hierarchy of an embedded system, a huge number of system simulations are needed for all the different instruction memory hierarchies, because many cache memory parameters should be explored. Exhaustive search of design space using simulation is too slow procedure and needs hundreds of simulations to find the optimal cache configuration. This chapter provides fast and accurate estimates of a multi-level instruction memory hierarchy. Using a detail methodology for estimating the number of instruction cache misses of the instruction cache levels and power models; we estimate within a reasonable time the power consumption among these hierarchies. In order to automate the estimation procedure, a novel software tool named FICA implements the proposed methodology, which automatically estimates the total energy in instruction memory hierarchy and reports the optimal one.


Cache Size Memory Hierarchy Cache Memory Control Flow Graph Assembly Code 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© IFIP 2010

Authors and Affiliations

  • Nikolaos Kroupis
    • 1
  • Dimitrios Soudris
    • 2
  1. 1.Department of Information and Telecommunication TechnologyTechnological Institute of LarisaLarisaGreece
  2. 2.School of Electrical & Computer Engineering, Department of Computer ScienceNational Technical University of AthensAthensGreece

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