Abstract
Statistical Static Timing Analysis (SSTA) is becoming necessary; but has not been widely adopted. One of those arguments against the use is that results of SSTA are difficult to make use of for circuit design. In this paper, by introducing conditional moments, we propose a path-based statistical timing approach, which permits us to consider gate topology and switching process induced correlations. With the help of this gate-to-gate delay correlation, differences between results of SSTA and those of Worst-case Timing Analysis (WTA) are interpreted. Numerical results demonstrate that path delay means and standard deviations estimated by the proposed approach have absolute values of relative errors respectively less than 5% and 10%.
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Wu, Z., Maurine, P., Azemard, N., Ducharme, G. (2010). Interpreting SSTA Results with Correlation. In: Monteiro, J., van Leuken, R. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2009. Lecture Notes in Computer Science, vol 5953. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-11802-9_6
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DOI: https://doi.org/10.1007/978-3-642-11802-9_6
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-11801-2
Online ISBN: 978-3-642-11802-9
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