Design of Reliable and Secure Multipliers by Multilinear Arithmetic Codes

  • Zhen Wang
  • Mark Karpovsky
  • Berk Sunar
  • Ajay Joshi
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5927)


We propose an efficient technique for the detection of errors in cryptographic circuits introduced by strong adversaries. Previously a number of linear and nonlinear error detection schemes were proposed. Linear codes provide protection only against primitive adversaries which no longer represents practice. On the other hand nonlinear codes provide protection against strong adversaries, but at the price of high area overhead (200–300%). Here we propose a novel error detection technique, based on the random selection of linear arithmetic codes. Under mild assumptions the proposed construction achieves near nonlinear code error detection performance at a lower cost (about 50% area overhead) due to the fact that no nonlinear operations are needed for the encoder and decoder.


Clock Cycle Error Detection Linear Code Information Part Fault Injection 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2009

Authors and Affiliations

  • Zhen Wang
    • 1
  • Mark Karpovsky
    • 1
  • Berk Sunar
    • 2
  • Ajay Joshi
    • 1
  1. 1.Reliable Computing LaboratoryBoston UniversityBostonUSA
  2. 2.CRIS LaboratoryWorcester Polytechnic InstituteWorcester01609

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